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LPS27HHTW 数据表(PDF) 6 Page - STMicroelectronics |
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LPS27HHTW 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 55 page  3.3 Communication interface characteristics 3.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and TOP. Table 5. SPI slave timing values Symbol Parameter Value(1) Unit Min. Max. tc(SPC) SPI clock cycle 100 ns fc(SPC) SPI clock frequency 10(2) MHz tsu(CS) CS setup time 6 ns th(CS) CS hold time 8 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time 50 th(SO) SDO output hold time 9 tdis(SO) SDO output disable time 50 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production. 2. Recommended to set max SPI clock 8 MHz to ≤50 Hz ODR. Figure 4. SPI slave timing diagram Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports. LPS27HHTW Communication interface characteristics DS13489 - Rev 1 page 6/55 |
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