LPS27HHTW datasheet(22/55 Pages) STMICROELECTRONICS

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7.2.1

I²C operation

The transaction on the bus is started through a START (ST) signal. A start condition is defined as a HIGH-to-LOW

transition on the data line while the SCL line is held HIGH. After the master has transmitted this, the bus is

considered busy. The next data byte transmitted after the start condition contains the address of the slave in the

first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the

slave. When an address is sent, each device in the system compares the first seven bits after a start condition

with its address. If they match, the device considers itself addressed by the master.

The 7-bit slave address (SAD) associated to the LPS27HHTW is 101110xb. The SDO/SA0 pad can be used to

modify the less significant bit of the device address. If the SA0 pad is connected to voltage supply, LSb is ‘1’ (7-bit

address 1011101b=5Dh), otherwise if the SA0 pad is connected to ground, the LSb value is ‘0’ (7-bit address

1011100b=5Ch). This solution permits connecting and addressing two different LPS27HHTW devices to the same

I²C lines.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge

pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the

acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each

byte of data received.

The I²C embedded inside the ASIC behaves like a slave device and the following protocol must be adhered to.

After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK), an

8-bit sub-address will be transmitted (SUB): the 7 LSB represent the actual register address while the MSB has

no meaning. The IF_ADD_INC bit in CTRL_REG2 (11h) enables sub-address auto increment (IF_ADD_INC is '1'

by default), so if IF_ADD_INC = '1' the SUB (sub-address) will be automatically increased to allow multiple data

read/write.

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition

must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with

direction unchanged. Table 11 explains how the SAD+read/write bit pattern is composed, listing all the possible

configurations.

Table 11. SAD+Read/Write patterns

Command

SAD[6:1]

SAD[0] = SA0

R/W

SAD+R/W

Read

101110

10111001 (B9h)

Write

101110

10111000 (B8h)

Read

101110

10111011 (BBh)

Write

101110

10111010 (BAh)

Table 12. Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 13. Transfer when master is writing multiple bytes to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 14. Transfer when master is receiving (reading) one byte of data from slave

Master

SAD + W

SUB

SAD + R

NMAK

Slave

SAK

DATA

LPS27HHTW

I²C serial interface (CS = high)

DS13489 - Rev 1

page 22/55

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