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LPS27HHTW 数据表(PDF) 35 Page - STMicroelectronics |
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LPS27HHTW 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 55 page ![]() 9.2 THS_P_L (0Ch) User-defined threshold value for pressure interrupt event (least significant bits) (R/W) 7 6 5 4 3 2 1 0 THS7 THS6 THS5 THS4 THS3 THS2 THS1 THS0 THS[7:0] This register contains the low part of threshold value for pressure interrupt generation. Default value: 00h The threshold value for pressure interrupt generation is a 15-bit unsigned right-justified value composed of THS_P_H (0Dh) and THS_P_L (0Ch).The value is expressed as: THS_P (15-bit unsigned) = Desired interrupt threshold (hPa) x 16 To enable the interrupt event based on this user-defined threshold, the DIFF_EN bit in INTERRUPT_CFG (0Bh) must be set to '1', the PHE bit or PLE bit (or both bits) in INTERRUPT_CFG (0Bh) has to be enabled. 9.3 THS_P_H (0Dh) User-defined threshold value for pressure interrupt event (most significant bits) (R/W) 7 6 5 4 3 2 1 0 - THS14 THS13 THS12 THS11 THS10 THS9 THS8 THS[14:8] This register contains the high part of threshold value for pressure interrupt generation. Default value: 00h Refer to THS_P_L (0Ch). 9.4 IF_CTRL (0Eh) Interface control register (R/W) 7 6 5 4 3 2 1 0 INT_EN_I3C 0 0 SDA_PU_EN SDO_PU_EN PD_DIS_INT1 I3C_DISABLE I2C_DISABLE INT_EN_I3C Enable INT1 pad with MIPI I3CSM. If the INT_EN_I3C bit is set, the INT1 pad is polarized as OUT. Default value: 0 (0: INT1 disabled with MIPI I3CSM; 1: INT1 enabled with MIPI I3CSM) SDA_PU_EN Enable pull-up on the SDA pin. Default value: 0 (0: SDA pin pull-up disconnected; 1: SDA pin with pull-up) SDO_PU_EN Enable pull-up on the SDO pin. Default value: 0 (0: SDO pin pull-up disconnected; 1: SDO pin with pull-up) PD_DIS_INT1 Disable pull down on the INT1 pin. Default value: 0 (0: INT1 pin with pull-down; 1: INT1 pin pull-down disconnected) I3C_DISABLE(1) Disable MIPI I3CSM interface. Default value: 0 (0: MIPI I3CSM enabled; 1: MIPI I3CSM disabled) I2C_DISABLE(2) Disable I²C interface. Default value: 0 (0: I²C enabled; 1: I²C disabled) 1. I3C_DISABLE bit disables the MIPI I3CSM communication protocol. 2. I2C_DISABLE bit disables the I²C interface, by default both SPI and I²C interfaces are enabled. LPS27HHTW THS_P_L (0Ch) DS13489 - Rev 1 page 35/55 |
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