LPS27HHTW datasheet(29/55 Pages) STMICROELECTRONICS

29 / 55 page

7.5

I²C/MIPI I3CSM coexistence in LPS27HHTW

In the LPS27HHTW, the SDA and SCL lines are common to both I²C and MIPI I3CSM. The I²C bus requires

anti-spike filters on the SDA and SCL pins that are not compatible with MIPI I3CSM timing.

The device can be connected to both I²C and MIPI I3CSM or only to the MIPI I3CSM bus depending on the

connection of the INT1 pin when the device is powered up:

•

INT_DRDY pin floating (internal pull-down): I²C/MIPI I3CSM both active, see Figure 23

–

I²C case: INT_DRDY pin is by default an input with pull-down. If I²C is used, INT_DRDY must be

left unconnected or eventually pulled down during device initialization. After power-on, during device

configuration, the INT_DRDY pin can be programmed as an interrupt output pin and it is recommended

to set bit I3C_disable to '1'.

–

I3C case: INT_DRDY pin is by default an input with pull-down. If I3C is used and the INT_DRDY pin is

unconnected, dynamic address assignment must be performed using I²C Fast Mode Plus Timing (max

1 MHz clock). After dynamic address assignment, I3C can be used in full speed mode.

•

INT_DRDY pin connected to Vdd_IO: only MIPI I3CSM active, see Figure 24

–

Only I3C: INT_DRDY pin is by default an input with pull-down. If INT_DRDY is set to Vdd_IO, I3C slave

is selected and device can be initialized at full speed through the SETDASA command. If the I3C bus

is available for more than 10 msec and the device is not yet addressed, a hot join request is performed

(SDA line kept to ground from slave) and the master must manage the request. After device address

assignment, a private write can be performed to disconnect the INT_DRDY pull-down.

Figure 23. I²C and MIPI I3CSM both active (INT_DRDY pin not connected)

I²C/I3C

(both active)

Master sends

I²C r/w

I²C bus case

Slave performs

requested r/w

Master assigns DA

to the slave(1)

I3C bus case

I3C private R/W with and without 7Eh

CCC commands

Slave event management

Error detection and recovery

Master resets

INT1 pin not connected

I²C/I3C both active

Address assignment (SETDASA) must be performed with I²C Fast Mode Plus Timing. When the slave is

addressed, the I²C slave is disabled and the timing is compatible with MIPI I3CSM specifications.

LPS27HHTW

I²C/MIPI I3CSM coexistence in LPS27HHTW

DS13489 - Rev 1

page 29/55

LPS27HHTW 数据表(PDF) 29 Page - STMicroelectronics

LPS27HHTW 数据表(HTML) 29 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

数据表下载