ADRF6806ACPZ-R7 datasheet(14/36 Pages) AD

14 / 36 page

ADRF6806

Data Sheet

Rev. B | Page 14 of 36

CIRCUIT DESCRIPTION

The ADRF6806 integrates a high performance IQ demodulator

with a state-of-the-art fractional-N PLL. The PLL also integrates

a low noise VCO. The SPI port allows the user to control the

fractional-N PLL functions, the demodulator LO divider functions,

and optimization functions, as well as allowing for an externally

applied LO.

The ADRF6806 uses a high performance mixer core that results

in an exceptional input IP3 and input P1dB, with a very low

output noise floor for excellent dynamic range.

LO QUADRATURE DRIVE

A signal at 2× the desired mixer LO frequency is delivered to

a divide-by-2 quadrature phase splitter followed by limiting

amplifiers which then drive the I and Q mixers, respectively.

V-TO-I CONVERTER

The differential RF input signal is applied to a V-to-I converter

that converts the differential input voltage to output currents. The

V-to-I converter provides a differential 100 Ω input impedance.

The V-to-I bias current can be reduced by putting the device in

low power mode (setting LPEN = 1 by setting Register 5, DB5 = 1).

Generally with LPEN = 1, input IP3 and input P1dB degrade,

but the noise figure is slightly better. Overall, the dynamic range

is reduced by setting LPEN = 1.

MIXERS

The ADRF6806 has two double-balanced mixers: one for the in-

phase channel (I channel) and one for the quadrature channel

(Q channel). These mixers are based on the Gilbert cell design

of four cross-connected transistors. The output currents from

the two mixers are summed together in the resistive loads that

then feed into the subsequent emitter follower buffers. When

the part is put into its low power mode (LPEN = 1), the mixer

core load resistors are increased, which does increase the gain by

roughly 3 dB; however, as previously stated in the V-to-I Converter

section, the overall dynamic range does decrease slightly.

EMITTER FOLLOWER BUFFERS

The output emitter followers drive the differential I and Q signals

off chip. The output impedance is set by on-chip 14 Ω series

resistors that yield a 28 Ω differential output impedance for each

baseband port. The fixed output impedance forms a voltage divider

with the load impedance that reduces the effective gain. For example,

a 500 Ω differential load has ~0.5 dB lower effective gain than a

high (10 kΩ) differential load impedance.

The common-mode dc output levels of the emitter follower

outputs are set by the voltage applied to the VOCM pin. The

VOCM pin must be driven with a voltage (typically 1.65 V) for

the emitter follower buffers to function. If the VOCM pin is left

open, the emitter follower outputs do not bias up properly.

BIAS CIRCUITRY

There are several band gap reference circuits and two low

droput regulators (LDOs) in the ADRF6806 that generate the

reference currents and voltages used by different sections. One of

the LDOs is the 2.5V_LDO, which is always active and provides

the 2.5 V supply rail used by the internal digital logic blocks.

The 2.5V_LDO output is connected to the DECL2 pin (Pin 9)

for the user to provide external decoupling. The other LDO is

the VCO_LDO, which acts as the positive supply rail for the

internal VCO. The VCO_LDO output is connected to the DECL1

pin (Pin 40) for the user to provide external decoupling. The

VCO_LDO can be powered down by setting Register 6, DB18 = 0,

which allows the user to save power when not using the VCO.

Additionally, the bias current for the mixer V-to-I stage, which

drives the mixer core, can be reduced by putting the device in

low power mode (setting LPEN = 1 by setting Register 5, DB5 = 1).

The ADRF6806 provides access to its many programmable features

through a 3-wire SPI control interface that is used to program

the seven internal registers. The minimum delay and hold times

are shown in the timing diagram (see Figure 2). The SPI provides

digital control of the internal PLL/VCO as well as several other

features related to the demodulator core, on-chip referencing,

and available system monitoring functions. The MUXOUT pin

provides a convenient, single-pin monitor output signal that can

be used to deliver a PLL lock-detect signal or an internal voltage

proportional to the local junction temperature.

Note that internal calibration for the PLL must run when the

ADRF6806 is initialized at a given frequency. This calibration is

run automatically whenever Register 0, Register 1, or Register 2 is

programmed. Because the other registers affect PLL performance,

last. For ease of use, starting the initial programming with

order ending with Register 0 is recommended. Once the PLL

and other settings are programmed, the user can change the

PLL frequency simply by programming Register 0, Register 1,

or Register 2 as necessary.

ADRF6806ACPZ-R7 数据表(PDF) 14 Page - Analog Devices

ADRF6806ACPZ-R7 数据表(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载