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ADRF6806ACPZ-R7 数据表(PDF) 15 Page - Analog Devices |
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ADRF6806ACPZ-R7 数据表(HTML) 15 Page - Analog Devices |
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15 / 36 page ![]() Data Sheet ADRF6806 Rev. B | Page 15 of 36 DIVIDE MODE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 00 00 00 00 00 00 0 DM ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0) DM 0 1 ID6 ID5 ID4 ID3 ID2 ID1 ID0 00 1 0 1 0 1 00 1 0 1 1 0 00 1 0 1 1 1 00 1 1 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 01 1 1 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 11 1 0 1 1 1 11 1 1 0 0 0 11 1 1 0 0 1 11 1 1 0 1 0 11 1 1 0 1 1 ... ... 119 120 (INTEGER MODE ONLY) DIVIDE RATIO 21 (INTEGER MODE ONLY) 22 (INTEGER MODE ONLY) 23 (INTEGER MODE ONLY) 24 ... ... 56 (DEFAULT) INTEGER INTEGER DIVIDE RATIO CONTROL BITS DIVIDE MODE FRACTIONAL (DEFAULT) 121 (INTEGER MODE ONLY) 122 (INTEGER MODE ONLY) 123 (INTEGER MODE ONLY) Figure 33. Integer Divide Control Register (R0) Register 0—Integer Divide Control With R0[2:0] set to 000, the on-chip integer divide control register is programmed as shown in Figure 33. The internal VCO frequency (fVCO) equation is fVCO = fPFD × (INT + (FRAC/MOD)) × 2 (1) where: fVCO is the output frequency of the internal VCO. INT is the preset integer divide ratio value (21 to 123 for integer mode, 24 to 119 for fractional mode). MOD is the preset fractional modulus (1 to 2047). FRAC is the preset fractional divider ratio value (0 to MOD − 1). The integer divide ratio sets the INT value in Equation 1. The INT, FRAC, and MOD values make it possible to generate output frequencies that are spaced by fractions of the PFD frequency. Note that the demodulator LO frequency is given by fLO = fVCO/M, where M is the programmed LO main divider (see Table 5). Divide Mode Divide mode determines whether fractional mode or integer mode is used. In integer mode, the VCO output frequency, fVCO, is calculated by fVCO = fPFD × (INT) × 2 (2) |
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