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24CS512 数据表(PDF) 29 Page - Microchip Technology |
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24CS512 数据表(HTML) 29 Page - Microchip Technology |
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29 / 66 page  2018-2021 Microchip Technology Inc. DS20005769C-page 29 24CS512 9.5 Locking the Configuration Register The locking mechanism of the Configuration register is controlled through the LOCK bit. The data of the confir- mation byte depends on the value being written to the LOCK bit. If the user intends to lock the Configuration register (LOCK = 1), the confirmation byte must be 99h. If the user intends to leave the register unlocked (LOCK = 0), the confirmation byte must be 66h. A mismatch of the LOCK bit and the confirmation byte will cause the operation to abort. Refer to Table 9-4 for additional information on the confirmation byte and the LOCK bit. Figure 9-3 illustrates the Configuration regis- ter lock sequence. FIGURE 9-3: CONFIGURATION REGISTER LOCK SEQUENCE Note: Once the Configuration register has been locked, it cannot be unlocked. Note: Locking the Configuration register cannot be inhibited by asserting the Write-Protect pin. Refer to Section 6.6 “Write Protec- tion”, which describes the device behavior with respect to the Write-Protect pin status. SCL MSb MSb MSb SDA 123 45 6 7 8 9 12 3 4 5 6 7 8 9 1 2 3 45 6 7 8 9 Word Address – Byte 1 Word Address – Byte 0 Device Address Byte 1 011 0 0 1 xx x1 0 x x 0 x x xx x x 0 xx A2 A1 A0 ACK from Client ACK from Client ACK from Client Start by Host MSb MSb MSb 1 2 3 4 5 6 78 9 1 2 3 45 6 7 8 9 1 2 3 456 7 8 9 CR Lock Configuration Register Configuration Register xx x x 0 1 D7 D6 D5 D4 D3 D2 D1 D0 01 0 0 1 1 0 0 01 xx D9 ACK from Client ACK from Client ACK from Client Stop by Host Confirmation Byte Byte 1 Byte 0 |
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