Enhanced Product

ADMV8818-EP

Rev. A | Page 27 of 36

REGISTER DETAILS

Note that the LUT1_SW to LUT127_FILTER bit fields functionality (Register 0x102 to Register 0x1FF) is identical to LUT0_SW and

LUT0_FILTER bit fields functionality (Register 0x100 and Register 0x101). See Table 6 for the register address information.

Address: 0x000, Reset: 0x00, Name: ADI_SPI_CONFIG_A

Soft Reset

Soft Reset

LSB First

LSB First

Endian

Endian

SDO Active

SDO Active

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

[7] SOFTRESET_ (R/W)

[0] SOFTRESET (R/W)

[6] LSB_FIRST_ (R/W)

[1] LSB_FIRST (R/W)

[5] ENDIAN_ (R/W)

[2] ENDIAN (R/W)

[4] SDOACTIVE_ (R/W)

[3] SDOACTIVE (R/W)

Table 7. Bit Descriptions for ADI_SPI_CONFIG_A

Bits

Bit Name

Description

Reset

Access

7

SOFTRESET_

Soft Reset.

0x0

R/W

0: reset asserted.

1: reset not asserted.

6

LSB_FIRST_

LSB First.

0x0

R/W

0: LSB first.

1: MSB first.

5

ENDIAN_

Endian.

0x0

R/W

0: Little Endian.

1: Big Endian.

4

SDOACTIVE_

SDO Active.

0x0

R/W

0: SDO inactive.

1: SDO active.

3

SDOACTIVE

SDO Active.

0x0

R/W

0: SDO inactive.

1: SDO active.

2

ENDIAN

Endian.

0x0

R/W

0: Little Endian.

1: Big Endian.

1

LSB_FIRST

LSB First.

0x0

R/W

0: LSB first.

1: MSB first.

0

SOFTRESET

Soft Reset.

0x0

R/W

0: Reset asserted.

1: Reset not asserted.