ADMV8818SCCZ-EP-R2 datasheet(15/36 Pages) AD

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Enhanced Product

ADMV8818-EP

Rev. A | Page 15 of 36

RFIN

RFOUT

Figure 33. HPF 1 Simplified Schematic

The HPF 2, HPF 3, and HPF 4 filters share the same architecture as

the HPF 1 filter. However, the filter order is increased with respect

to the frequency to achieve a similar rejection response for all

filters.

TUNABLE LOW-PASS FILTERS

Figure 34 shows a simplified schematic of the LPF 1, which is a

Chebyshev type filter. The f3dB can be adjusted by varying

Capacitor C1 to Capacitor C4. These tunable capacitors are

constructed with 4-bit digital capacitor arrays, providing 16

distinct values. The step size of these tunable capacitors is

adjusted so that each digital binary code increment creates

approximately the same increment in the f3dB.

RFIN

RFOUT

Figure 34. LPF 1 Simplified Schematic

The LPF 2, LPF 3, and LPF 4 filters share the same architecture as

the LPF 1 filter. However, the filter order is increased with respect

to the frequency to achieve a similar rejection response for all

filters.

SPI CONFIGURATION

The SPI of the ADMV8818-EP allows configuration of the

device for specific functions or operations via the 5-pin SPI

port. This interface provides users with added flexibility and

customization. The SPI consists of five control lines: SFL, SCLK,

SDI, SDO, and CS. For normal SPI operations, keep the SFL pin

low.

The SPI protocol consists of an R/W bit followed by 15 register

address bits and 8 data bits. The address field and data field are

organized MSB first and end with the LSB.

Set the MSB to 0 for a write operation and set the MSB to 1 for a

read operation. The write cycle must be sampled on the rising

edge of SCLK. The 24 bits of the serial write address and data are

shifted in on the SDI control line, MSB to LSB. The ADMV8818-

EP input logic level for the write cycle supports a 3.3 V

interface.

For a read cycle, the R/W bit and the 15 register address bits

shift in on the rising edge of SCLK on the SDI control line. Then,

8 bits of serial read data shift out on the SDO control line, MSB

first, on the falling edge of SCLK. The output logic level for a

read cycle is 3.3 V. The output drivers of the SDO are enabled

after the last rising edge of SCLK of the instruction cycle and

remain active until the end of the read cycle. In a read operation,

when CS is deasserted, SDO returns to high impedance until the

next read transaction. CS is active low and must be deasserted

at the end of the write or read sequence.

An active low input on CS starts and gates a communication

cycle. The CS pin allows more than one device to be used on

the same serial communications lines. The SDO pin goes to a

high impedance state when the CS input is high. During the

communication cycle, the chip select must stay low. The SPI

communications protocol follows the Analog Devices SPI

standard. For more information, see the ADI-SPI Serial

Control Interface Standard (Rev 1.0).

RF CONNECTIONS

The RFIN and RFOUT pins of the ADMV8818-EP are dc-

coupled to on-chip RF switches. If a dc voltage is present on the

RFIN and RFOUT pins from other components within the

system, it is recommended to place dc blocking capacitors in series

with these pins. The dc blocking capacitors must be selected

based on the operating frequency of the filter. Generally, a

value greater than 100 pF is sufficient to minimize insertion

loss at the lower frequencies of operation. At higher frequencies

of operation, it may be necessary to consider the parasitic elements

of the selected capacitor. Figure 35 shows a general model of a

capacitor with the parasitic elements. The parasitic series

inductance (LESL) is typically of most concern given that its

impedance can become dominant at frequencies above 10 GHz.

The other parasitic elements, including the leakage resistance

(RL), the dielectric absorption resistance (RDA), the dielectric

absorption capacitance (CDA), and electrical series resistance (RESR)

are less critical elements for consideration but are shown here for

completeness.

LESL

RESR

RDA CDA

Figure 35. General Model of a Capacitor

MODE SELECTION

The ADMV8818-EP has two modes of operation: SPI write and

SPI fast latch. SPI write mode is the normal operating mode,

whereas SPI fast latch mode is used to sequence through the

on-chip lookup table (LUT) using the internal state machine.

To select SPI write mode, set the SFL pin low. For operation in

SPI fast latch mode, program the on-chip lookup table and fast

latch parameters with the SFL pin low, and then bring the SFL

pin high to enter this mode. Figure 36 shows a simplified

representation of the SPI with the register map and internal

state machine.

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