ADMV8818SCCZ-EP-R2 datasheet(17/36 Pages) AD

17 / 36 page

Enhanced Product

ADMV8818-EP

Rev. A | Page 17 of 36

latch mode is enabled, and the internal state machine sequences

on each rising edge of the CS pin.

The lookup table has 128 groupings, LUT0 through LUT127, in

of the same type of parameters as those of SPI write mode.

The functionality of the switch positions and filter state bits for

SPI fast latch mode is similar to those of SPI write mode. That is,

the filter state bits are assigned based on the switch position bits.

However, the switch set parameters do not contain any priority.

If the RFIN switch set bits and RFOUT switch set bits are

enabled for a particular LUT, the switch positions change.

The functionality of the internal state machine is such that on

each rising edge of the CS pin, the internal state machine sequences

a pointer based on the programmed direction. The internal

state machine has the following parameters:

•

FAST_LATCH_POINTER (Register 0x010)

•

FAST_LATCH_LOAD (Register 0x010)

•

FAST_LATCH_STOP (Register 0x011)

•

FAST_LATCH_START (Register 0x012)

•

FAST_LATCH_DIRECTION (Register 0x013)

•

FAST_LATCH_STATE (Register 0x014)

The FAST_LATCH_STATE is the next LUT grouping that is

selected on the next rising edge of the CS pin. The FAST_LATCH_

STATE is considered the internal pointer location.

The internal pointer location can be changed by using the FAST_

LATCH_LOAD and FAST_LATCH_POINTER bits. When the

FAST_LATCH_LOAD bit is set high, the FAST_LATCH_

POINTER value is loaded into the internal pointer. The FAST_

LATCH_LOAD bit is self resetting after the load operation

completes.

When the FAST_LATCH_DIRECTION bit is set to zero, the

sequencing direction is incremental. When the FAST_LATCH_

DIRECTION bit is set to one, the sequencing direction is

decremental.

The FAST_LATCH_START and FAST_LATCH_STOP bits are

used to set the start and stop location, respectively. For incremental

direction, the internal state machine sequences from the start

location to the stop location and then rolls over to the start

location. For the decremental direction, the sequence is from

the stop location to the start location and then rolls over to the

stop location.

The FAST_LATCH_STATE value can fall outside of the start

and stop locations, which occurs if the start and stop locations

are updated and the internal pointer is left unchanged from its

prior value. If this situation occurs, additional LUT groupings

are selected before the FAST_LATCH_STATE value eventually

falls within the start and stop locations. For example, if the FAST_

LATCH_STATE value is 12, the direction is incremental, the start

location is 15, and the stop location is 31, the LUT groupings

selected on the next six rising edges of the CS pin are the LUT

grouping numbers, 12, 13, 14, 15, 16, and 17.

CHIP RESET

There are two methods that can be used to reset the ADMV8818-

EP registers to their default power-on state, a hard reset and a

soft reset. The hard reset utilizes the RST pin, and the soft reset

utilizes Register 0x000.

To perform a hard reset, momentarily bring the RST pin low

and then high. See Figure 2 for the minimum required duration

time for the RST pin to be low.

To perform a soft reset, program Register 0x000 to a value of 0x81.

This action sets the SOFTRESET and SOFTRESET_ bits high to

initiate the reset. The SOFTRESET and SOFTRESET_ bits are

self resetting once the reset operation is complete.

Regardless of the reset method used, it is recommended to

perform the following after the chip resets:

•

Program Register 0x000 to 0x3C to enable the SDO pin

and allow SPI streaming with Endian ascending order.

•

Read back all registers on the chip.

ADMV8818SCCZ-EP-R2 数据表(PDF) 17 Page - Analog Devices

ADMV8818SCCZ-EP-R2 数据表(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载