ADRF6521ACPZ-R7 datasheet(29/33 Pages) AD

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Data Sheet

ADRF6521

Rev. 0 | Page 29 of 33

THEORY OF OPERATION

The ADRF6521 is a highly linear, dual channel VGA with a

−3 dB frequency response of 3.25 GHz. The ADRF6521 consists

of a matched pair of VGAs, each consisting of a voltage variable

attenuator (VVA) designed to have 21 dB of attenuation range

at room temperature (TA = 25°C), followed by an 18 dB

amplifier, producing a gain range from +18 dB to −3 dB.

The output stage has the ability to change its common-mode

voltage and have a purposeful dc offset voltage. The output

common-mode voltage range and output dc offset voltage range

are adjustable up to ±200 mV and ±400 mV, respectively, while

still maintaining the high linearity outlined in Table 1. Larger

ranges are possible, but linearity degrades. Figure 120 shows the

simplified block diagram of a single channel.

18dB

20dB

VVA

– +

OUTPUTS

OFSx

VOCM

ANALOG

GAIN CONTROL

45mV/dB

INPUTS

VGN

Figure 120. Simplified Functional Block Diagram for a Single Channel

The entire differential signal chain is dc-coupled. However it is

recommended to ac-couple the input signal paths. The gain setting

control for the two channels is a shared pin (VGN), ensuring close

matching of their magnitude and phase responses. The ADRF6521

is fully disabled by pulling PWD to the VNEG supply.

INPUT VVAs

The input VVAs are designed to have high linearity and excellent

log conformance. The VVAs have a differential input impedance

of 100 Ω and an attenuation range of 21 dB, which decreases

slightly over temperature. If the input must be dc-coupled, the

output common mode of the previous stage must match the

voltage on the VOCM pin. The topology of an input VGA, for

example, the VVA located at the input of the device, is such that

the noise figure degrades dB for dB as attenuation increases. The

VVA maintains its high linearity across its full range of attenuation.

AMPLIFIERS

The ADRF6521 amplifiers use the same core as the ADL5569.

The amplifiers have a low output impedance (<20 Ω), and the

RF to RG on-chip resistor ratio is approximately 8×, which creates

the 18 dB of differential voltage gain. The amplifiers are designed to

drive subsequent amplifier stages and are capable of high linearity

with 1.5 V p-p two-tone signals into 100 Ω differential loads.

OUTPUTS

ADL5569

CORE

FROM

VVA

= 8

AV =

Figure 121. 18 dB Amplifier for a Single Channel

OUTPUT COMMON-MODE VOLTAGE

The output common-mode voltage is set internally to (VPOS +

VNEG)/2, with an on-chip resister divider (see Figure 122). This

voltage can be adjusted ±200 mV via the VOCM pin and the

ADRF6521 still maintains IMD2, IMD3, HD2, and HD3 of

−55 dBc or better. There is a 1 to 1 mapping between the control

voltage applied to VOCM and the output common-mode voltage.

2.5kΩ

VOCM

VPOS

VNEG

OUTPUT

COMMON-MODE

CONTROL CIRCUITRY

2.5kΩ

Figure 122. VOCM Simplified Circuit

OUTPUT DC OFFSET CIRCUIT

The output dc offset on each channel of the ADRF6521 can be

independently nulled out to account for the small inherent dc

offsets of the VVA and amplifier. For applications such as

predistortion, the output dc offset voltage of each channel can

intentionally be increased up to ±400 mV in addition to the

±200 mV output common-mode range, while still maintaining

high linearity. Adjusting the output common-mode and the

output dc offset voltage more than a combined 400 mV from

the nominal voltage on any output pin causes the linearity to

degrade, possibly to IMDx and/or HDx levels worse than −55 dBc.

The output dc offset voltage is defined as follows:

VOFS_DC = VOPPx − VOPMx

where VOPPx and VOPMx are the dc voltages on the OPP1 and

OPM1 or the OPP2 and OPM2 output pins.

The output dc offset voltage is controlled via the OFS1 pin and

OFS2 pin, shown in Figure 120 and Figure 124 as a generic

OFSx pin. The output dc offset voltage is fundamentally caused

by injecting a differential current into the input of the amplifier.

The differential current consists of the following:

•

A reference current (IREF), which is added to both the

positive and negative legs of the differential path

•

A bipolar offset current (IOFS), which is added on one leg of

the differential path and subtracted from the other leg

The reference current is a static current, but the bipolar offset

current is controlled via the respective OFSx pins. Both currents

are injected between the 18 dB amplifier and VVA. Because the

offset current is bipolar, the output dc offset voltage goes up to

+400 mV or down to −400 mV. The nominal closed form

equation between the control voltage on the FLTx pins and the

output dc offset voltage is

VDC_OFFSET_DIFF = 0.89 × VOFSx − 0.668 V

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