ADRF6521

Data Sheet

Rev. 0 | Page 8 of 33

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

14

13

12

1

3

4

OPP1

15 OPM1

VOCM

OPP2

11 OPM2

INM1

COMM

2

INP1

INP2

5

INM2

6 7 8 9 10

20 19 18 17 16

ADRF6521

TOP VIEW

(Not to Scale)

NOTES

1. EXPOSED PAD. THE EXPOSED PAD IS INTERNALLY

CONNECTED TO VNEG AND MUST BE SOLDERED

TO THE NEGATIVE SUPPLY RAIL.

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2

INM1, INP1

Channel 1 Differential Inputs, 100 Ω Differential Input Impedance. (VPOS + VNEG)/2 nominal common mode.

3

COMM

Analog Ground.

4, 5

INP2, INM2

Channel 2 Differential Inputs, 100 Ω Differential Input Impedance. (VPOS + VNEG)/2 nominal common mode.

6

OFS2

Channel 2 Output DC Offset Control. Nominal control range from 0.3 V to 1.2 V relative to analog ground. A 0.75 V

on OFSx produces a 0 V output offset voltage. OFS2 is not self biased. OFS2 must be driven. Left unconnected,

OFS2 is pulled to ground via an on-chip 5 kΩ resistor, which forces the output dc offset to be −700 mV. Voltages

greater than 1.5 V but less than the absolute maximum ratings may cause latch-up.

7

FLT2

Channel 2 Filter Pin. Connect FLT2 to the negative supply via a 1 µF capacitor.

8, 18

VNEG

Analog Negative Supply Voltage. For single-supply operation, set VNEG to 0 V nominal, and for dual-supply

operation, set VNEG to −2 V nominal. Keep (VPOS − VNEG) ≤ 5 V, VNEG ≤ COMM ≤ VPOS, and −2.5 V ≤ VNEG ≤ 0 V

to keep the voltage at the allowable pin voltage related to the voltage on the VPOS pin. Pins are electrically connected

on chip and to the exposed pad. Connect both VNEG pins and the exposed pad to the negative supply voltage.

9

PWD

Chip Power Down. Pull to VNEG supply to disable both channels. Leave unconnected to enable. Keep V

(VNEG + 3.3 V).

10, 16

VPOS

Analog Positive Supply Voltage. For single-supply operation, set VPOS to 5 V nominal, and for dual-supply

operation, set VPOS to 3 V nominal. Keep (VPOS − VNEG) ≤ 5 V, VNEG ≤ COMM ≤ VPOS, and VPOS ≥ 2.3 V to keep

the voltage at the allowable pin voltage related to the voltage on the VNEG pin. Pins are electrically connected

on chip. Connect both VPOS pins to the positive supply voltage.

11, 12

OPM2, OPP2

Channel 2 Differential Outputs. These outputs have a 16 Ω differential output impedance.

13

VOCM

Output Common-Mode Voltage Control. The nominal control range is (VPOS + VNEG)/2 − 200 mV to (VPOS +

VNEG)/2 + 200 mV. A 0 V on VOCM is a 0 V output common-mode voltage. Self biased to (VPOS + VNEG)/2.

14, 15

OPP1, OPM1

Channel 2 Differential Outputs. These outputs have a 16 Ω differential output impedance.

17

VGN

VGA Analog Gain Control. The VGN pins operate from 0 V to 1.5 V with 45 mV/dB gain scaling. Voltages greater

than 1.5 V but less than the absolute maximum ratings may cause latch-up.

19

FLT1

Channel 1 Filter Pin. Connect FLT1 to a negative supply via a 1 µF capacitor.

20

OFS1

Channel 1 Output DC Offset Control. Nominal control range from 0.3 V to 1.2 V relative to analog ground. A 0.75 V

on OFSx produces a 0 V output offset voltage. OFS1 is not self biased. OFS1 must be driven. Left unconnected,

OFS1 is pulled to ground via an on-chip 5 kΩ resistor, which forces the output dc offset to be −700 mV.

EP

Exposed Pad. The exposed pad is internally connected to VNEG and must be soldered to the negative supply rail.