ADRF6521ACPZ-R7 datasheet(30/33 Pages) AD

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ADRF6521

Data Sheet

Rev. 0 | Page 30 of 33

DC Offset Loop High-Pass Corner

The ADRF6521 has dc offset loops that null any signal below

their low-pass frequency corner, which is set by a combination

of the internal 35 pF capacitor plus any external capacitor

decoupled to VNEG from OFSx.

Although the dc offset loops have a low-pass response, the signal

paths show a high-pass response because the loops null any low

frequency signal below their low-pass corner. The following

equation shows the relationship between the high-pass corner

observed on the signal paths and the value of the external

capacitor decoupled to VNEG, which is called COFS:

fHP (Hz) = 60/(COFS (µF) + 35 × 10−6)

With COFS = 1 µF, the high-pass corner in Hz is calculated as:

fHP (Hz) = 60/(1 + 35 × 10−6) = 60 Hz

The feedback loop shown in Figure 124 creates the output dc

offset voltage. The differential to single-ended amplifier samples

the differential output, converts the signal into single-ended mode,

and averages the signal with a capacitor connected to VNEG.

This averaged version of the output is compared to the dc voltage

applied to the OFSx pin(s) with the transconductance amplifier

(gm). The output differential current of the gm stage is injected

between the RF and RG resistors of the 18 dB amplifier. The

feedback loop forces the differential current of the gm amplifier to

increase or decrease until the averaged voltage from the differential

to single-ended amplifier is equal to the applied OFSx voltage.

This differential current injected at the input of the amplifier

creates an intentional dc offset voltage at the input, which is

then amplified and seen on the output pins, OPPx and OPMx.

The output dc offset circuits are filtered on each channel via the

FLT1 and FLT2 pins, for Channel 1 and Channel 2, respectively.

Connect both pins to the negative supply via a 1 µF capacitor.

There is an on-chip capacitance of 35 pF on each FLTx node.

GAIN CONTROL INTERFACE

The ADRF6521 has a linear-in-dB gain control interface. The

gain control slope is maintained at 22.2 dB/V over temperature,

supply, and process as gain varies from 250 mV to 1200 mV.

The gain function is given by

Gain (dB) = 22.2 × VVGN – 8.5

where VVGN is the voltage on the VGN gain pin in volts.

The gain control voltage range is from 0 V to 1.5 V, with respect

to analog ground.

POWER-DOWN FUNCTION

The power-down function is accomplished via the PWD pin. By

default, the device is enabled via the resistive divider shown in

Figure 123. Assert the PWD pin to the same potential as VNEG

to reduce the current consumption to roughly 25 mA. Do not

apply a voltage more than VNEG + 3.3 V on the PWD pin.

Higher voltages may cause damage to the device.

20kΩ

VPOS

VNEG

PWD

POWER-DOWN

CONTROL CIRCUITRY

30kΩ

Figure 123. Simplified Power Down Interface

OUTPUTS

IREF ± (–IOFS)

IREF ± IOFS

ADL5569

CORE

FROM

VVA

35pF

VNEG

FLTx

OFSx

5kΩ

DIFFERENTIAL TO

SINGLE-ENDED

AMPLIFIER

Figure 124. Output DC Offset Circuit for a Single Channel

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