ADRF6521ACPZ-R7 datasheet(32/33 Pages) AD

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ADRF6521

Data Sheet

Rev. 0 | Page 32 of 33

ENABLE AND DISABLE FUNCTION

To enable the ADRF6521, leave the PWD pin open or pull this

pin to VNEG + 3.0 V. Driving the PWD pin to VNEG disables

the device, reducing the current consumption to approximately

25 mA at room temperature.

GAIN PIN (VGN) DECOUPLING

The ADRF6521 has one analog gain control pin, VGN. The gain

changes when an applied VGN voltage is between 0 V and 1.5 V.

Maximum voltage on the VGN pin is equal to the voltage applied

to VPOS. Use at least one low inductance, surface-mount

ceramic capacitor with a value of 0.1 µF and one 1000 pF in

parallel to ground on the gain pin (VGN) to decouple to ground.

OUTPUT IMPEDANCE MATCHING

The ADRF6521 natively has a low differential output impedance

of ≤16 Ω. Depending on the PCB design of the user and the S22

requirements, matching the output impedance to 100 Ω differential

may be desirable. To achieve a match looking towards the output

pins, place a pair of 43 Ω series resistors as close as possible to

the output pins (OPP1, OPM1, OPP2, and OPM2).

The installation of these 43 Ω resistors decreases the voltage level

of the signal by roughly 6 dB, and thus decreases the maximum

gain of the VGA to 12 dB. This loss of signal level is usually

acceptable because of the high linearity of the ADRF6521. That

is, the ADRF6521 can operate at twice the output signal level

(with respect to no matching resistors), and still maintain

−55 dBc IMD2 and IMD3 and HD2 and HD3 levels or better.

Note that when using series matching resistors, the output dc

offset voltage is also reduced by the same amount as the RF

signal level.

If a full 100 Ω match is not required and a greater than 12 dB

gain value is more important, the user can decrease the series

resistor value until an optimum trade-off between the gain and

the output match is found.

SINGLE-SUPPLY OPERATION

The ADRF6521 can operate on a 5 V single supply. Connect

VNEG to analog ground. The output common-mode voltage

defaults to 2.5 V in this configuration. The nominal range of

±200 mV still applies. A larger range is possible, however,

linearity performance degrades.

DUAL-SUPPLY OPERATION

Apply a nominal supply voltage of +2.5 V to the VPOS supply

pin, and −2.5 V to the VNEG supply pin. This setup yields a

nominal output common-mode voltage of 0 V, and the output

dc offset voltage moves above and below ground according to

what voltage is applied to the OFSx pins.

When using a dual supply, ensure the following supply

constraints:

•

4 V ≤ (VPOS − VNEG) ≤ 5 V.

•

VNEG ≤ COMM ≤ VPOS

•

VPOS ≥ 2.5 V

AVOIDING LATCH-UP

To avoid latch-up when the device is operational or when the

device is powering up, do not apply a voltage greater than the

following:

•

1.5 V (relative to ground) to the control pins (VGN, OFS1,

and OFS2).

•

(VVPOS + VVNEG)/2 ± 1 V to the control pin VOCM

If the RF input must be dc coupled, the common-mode voltage

must be the same as the VOCM pin voltage, which must be

limited to (VPOS + VNEG)/2 ± 0.2 V. If while powered down

and dc coupled a dc voltage with a magnitude greater than

(VPOS + VNEG)/2 ± 0.2 V is applied, this dc voltage must

return within the common-mode limit before powering up the

ADRF6521.

ADRF6521ACPZ-R7 数据表(PDF) 32 Page - Analog Devices

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