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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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56F8335 数据表(PDF) 59 Page - Freescale Semiconductor, Inc |
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56F8335 数据表(HTML) 59 Page - Freescale Semiconductor, Inc |
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59 / 160 page  Peripheral Memory Mapped Registers 56F8335 Technical Data, Rev. 1 Freescale Semiconductor 59 Preliminary Table 4-28 Clock Generation Module Registers Address Map (CLKGEN_BASE = $00 F2D0) Register Acronym Address Offset Register Description PLLCR $0 Control Register PLLDB $1 Divide-By Register PLLSR $2 Status Register Reserved SHUTDOWN $4 Shutdown Register OSCTL $5 Oscillator Control Register Table 4-29 GPIOA Registers Address Map (GPIOA_BASE = $00 F2E0) Register Acronym Address Offset Register Description Reset Value GPIOA_PUR $0 Pull-up Enable Register 0 x 3FFF GPIOA_DR $1 Data Register 0 x 0000 GPIOA_DDR $2 Data Direction Register 0 x 0000 GPIOA_PER $3 Peripheral Enable Register 0 x 3FFF GPIOA_IAR $4 Interrupt Assert Register 0 x 0000 GPIOA_IENR $5 Interrupt Enable Register 0 x 0000 GPIOA_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOA_IPR $7 Interrupt Pending Register 0 x 0000 GPIOA_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOA_PPMODE $9 Push-Pull Mode Register 0 x 3FFF GPIOA_RAWDATA $A Raw Data Input Register — |
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