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56F8335 数据表(PDF) 83 Page - Freescale Semiconductor, Inc |
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56F8335 数据表(HTML) 83 Page - Freescale Semiconductor, Inc |
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83 / 160 page  Register Descriptions 56F8335 Technical Data, Rev. 1 Freescale Semiconductor 83 Preliminary 5.6.7 Interrupt Priority Register 6 (IPR6) Figure 5-9 Interrupt Priority Register 6 (IPR6) 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.7.2 Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.7.3 Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TMRC0 IPL TMRD3 IPL TMRD2 IPL TMRD1 IPL TMRD0 IPL 0 0 DEC0_XIRQ IPL DEC0_HIRQ IPL Write RESET 00000 0000000 0000 |
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