ADP1972

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ADP1972

TOP VIEW

(Not to Scale)

DH

VREG

VIN

SYNC

MODE

EN

DL

FAULT

GND

SCFG

SS

COMP

DMAX

FREQ

CL

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

DL

Logic Drive Low Output for External Low-Side MOSFET Driver.

2

DH

Logic Drive High Output for External High-Side MOSFET Driver.

3

VREG

Internal Low Dropout (LDO) Voltage Regulator Output and Internal Bias Supply. A bypass capacitance of 1 µF or

greater from this pin to ground is required.

4

VIN

High Input Voltage Supply Pin. Bypass this pin with a 4.7 µF capacitor to ground.

5

EN

Logic Enable Input. Drive EN logic low to shut down the device. Drive EN logic high to turn on the device.

6

MODE

Mode Select. Drive MODE logic low to place the device in boost/recycle mode. Drive MODE logic high to place

the device in buck/charge mode of operation.

7

SYNC

Synchronization Pin. This pin is used as an input and synchronized to an external clock or used as an output

clock to synchronize with other channels.

8

FAULT

Fault Input Pin. Signaled by an overcurrent protection (OCP) or overvoltage protection (OVP) fault condition on

the companion ASIC, AD8450. The ADP1972 is disabled until this pin is logic high.

9

COMP

Output Error Amplifier Signal from the companion ASIC, AD8450. This pin is the error input to the ADP1972 and

is compared internally to the linear ramp to produce the PWM signal. Do not leave this pin floating.

10

SS

Soft Start Control Pin. A capacitor connected from SS to ground brings the output up slowly during power-up

and reduces the inrush current.

11

DMAX

Maximum Duty Cycle Input. Connect an external resistor to ground to set the maximum duty cycle. If the 98%

internal maximum duty cycle is sufficient for the application, tie this pin to VREG. If DMAX is left floating, this

pin is internally tied to VREG.

12

FREQ

Frequency Set Pin. Connect an external resistor between this pin and ground to set the frequency between

50 kHz and 300 kHz.

13

SCFG

phase shift so that it synchronizes the device to an external clock source. If SCFG is left floating, the SYNC pin

is internally tied to VREG, and SYNC is configured as an output.

14

GND

Power and Analog Ground Pin.

15

Ground Sense for the Current-Limit Setting Resistor.

16

CL

Current-Limit Programming Pin. Connect a current-limit sense resistor in series with the FET source to set the

peak current limit.

Rev. B | Page 6 of 18