ADP1972

Data Sheet

APPLICATIONS INFORMATION

The ADP1972 has many programmable features that are

optimized and controlled for a given application. The ADP1972

provides pins for selecting the operating mode, controlling the

current limit, selecting an internal or external clock, setting the

operating frequency, phase shifting the operating frequency,

programming the maximum duty cycle, and adjusting the

soft start.

BUCK OR BOOST SELECTION

To operate the ADP1972 in boost/recycle mode, apply a voltage

less than 1.05 V (typical) to the MODE pin. To operate the

ADP1972 in buck/discharge mode, drive the MODE pin high,

greater than 1.2 V (typical). The state of the MODE pin can

only be changed when the ADP1972 is shutdown via the EN

pin, or disabled via an external fault condition signaled on the

FAULT pin, a TSD event, or a UVLO condition.

See Figure 21 for the current-limit block diagram for peak

current-limit control. Use using the following equation to set

the current limit:

(

)

S

PK

R

I

mV

100

mA =

(1)

where:

When the ADP1972 is configured to operate in buck/charge

mode, the internal current-limit reference is set to 300 mV

(typical). When the ADP1972 is configured to operate in

boost/recycle mode, the internal current-limit reference is set to

the current properly to detect the peak in both buck and boost

equation for setting the peak current follows:

For buck/charge mode, it is

(2)

For boost/recycle mode, it is

(3)

where:

The ADP1972 is designed so that the peak current limit is

the same in both the buck mode and boost mode of operation.

recommended.

ADJUSTING THE OPERATING FREQUENCY

SCFG is left floating and internally tied to VREG, the ADP1972

output clock on the SYNC pin can be used as a master clock in

applications that require synchronization.

and the ADP1972 operates as a slave device. As a slave device,

the ADP1972 synchronizes to the external clock applied to

the SYNC pin. If the voltage applied to the SCFG pin is

SCFG and ground, the SYNC pin is configured as an input,

and the ADP1972 synchronizes to a phase shifted version of the

external clock applied to the SYNC pin.

Whether operating the ADP1972 as a master or as a slave

the following sections.

When functioning as a master device, the ADP1972 operates at

FREQ and ground, and the ADP1972 outputs a clock at the

programmed frequency on the SYNC pin.

Figure 22 shows the relationship between the programmed

210

30

50

70

90

110

130

150

170

190

50

100

150

200

250

300

desired master clock synchronization frequency:

( )

(kHz)

10

kΩ

4

)

(

SET

MASTER

FREQ

f

R

=

(4)

where:

devices.

Rev. B | Page 14 of 18