Data Sheet

ADP1972

Rev. B | Page 15 of 18

When functioning as a slave device, the ADP1972 operates at

the frequency of the external clock applied to the SYNC pin. To

to a value slightly slower than that of the master clock by using

the following equation:

(5)

where:

frequency of the master clock applied to the SYNC pin.

master ratio for synchronization.

The frequency of the slave device is set to a frequency slightly

lower than that of the master device to allow the digital

synchronization loop of the ADP1972 to synchronize to the

master clock period. The slave device has approximately a 30%

range capability to adjust to match the master clock value.

synchronization loop in approximately the center of the

adjustment range.

Programming the External Clock Phase Shift

If a phase shift is not required for slave devices, connect SCFG

of each slave device to ground. For devices that require a phase

shifted version of the synchronization clock that is applied to

from SCFG to ground to program the desired phase shift. To

)

FREQ(SLAVE

SLAVE

R

f

4

10

(kHz) 

(6)

Next, calculate the period of the slave clock.



3

10

(kHz)

1

μs





SLAVE

SLAVE

f

T

(7)

where:



 

360

μs

φ

μs

SLAVE

SHIFT

DELAY

T

T





(8)

where:

equation:

(9)

where:

in kHz.

When using the phase shift feature, connect a capacitor of 47 pF

Alternatively, the SCFG pin can be controlled with a voltage

source. When using an independent voltage source, ensure

disabled via the EN pin or UVLO, VREG = 0 V, and the voltage

Figure 23 shows the internal voltage ramp of the ADP1972. The

voltage ramp has a well controlled 4 V p-p.

4.5V

T

0.5V

0.01T

0.99T

Figure 23. Internal Voltage Ramp

PROGRAMMING THE MAXIMUM DUTY CYCLE

The ADP1972 is designed with a 98% (typical) internal

maximum duty cycle. By connecting a resistor from DMAX to

ground, the maximum duty cycle can be programmed at any

value from 0% to 98%, using the following equation:



5

.

10

5

.

21

%









FREQ

DMAX

FREQ

MAX

R

R

V

D

(10)

where:

maximum duty cycle.

The current source of DMAX is equivalent to the programmed

current of the FREQ pin:

FREQ

FREQ

FREQ

DMAX

R

V

I

I





(11)

FREQ pin.

The maximum allowable duty cycle of the ADP1972 is 98%

(typical). If the resistor on DMAX sets a maximum duty cycle

larger than 98%, the ADP1972 defaults to its internal

maximum. If the 98% internal maximum duty cycle is sufficient

for the application, tie the DMAX pin to VREG or leave it floating.

must be 47 pF or greater.