ADP1972

Data Sheet

THEORY OF OPERATION

FREQ

SYNC

VIN

SYNC

DETECT

5µA

VREG

COMP

SS

FAULT

EN

ADP1972

VREG

AD8450

AD8450

DMAX

SCFG

GND

TSD

VREG

UVLO

BAND GAP

MODE

VREG

DH

DL

DRIVE

LOGIC

OSCILLATOR

CONFIG

DETECT

CL

VREG

EXTERNAL

DRIVER

5V

15V

24V

VOUT

500mV

300mV

MODE

SELECT

4V

20µA

MODE

SELECT

PGND

AGND

1MΩ

1MΩ

1

MΩ

20kΩ

4.7µF

1µF

L

M1

M2

VREG = 5V

VREG

8.5MΩ

Figure 16. Block Diagram

The ADP1972 is a constant frequency, voltage mode, PWM

controller for buck or boost, dc-to-dc, asynchronous

applications with an external, high voltage FET, half bridge

driver, and an external error signal generating device, such as

the AD8450. The ADP1972 has a high input voltage range,

multiple externally programmed control pins, and integrated

safety features.

SUPPLY PINS

The ADP1972 has two voltage supply pins, VIN and VREG.

The VIN pin operates from an external supply that ranges from

6 V to 60 V and is the supply voltage for the internal LDO

regulator of the ADP1972. Bypass the VIN pin to ground with a

4.7 µF or greater ceramic capacitor.

The VREG pin is the output of the internal LDO regulator. The

internal LDO regulator generates the 5 V (typical) rail that is

used internally to bias the control circuitry and can be used

externally as a pull-up voltage for the MODE, SYNC, DMAX,

and FAULT pins. Bypass the VREG pin to ground with a 1 µF

ceramic capacitor.

When operating with an input voltage above 50 V, additional

input filtering is necessary. Figure 17 shows the recommended

filter configuration.

VIN

SUPPLY > 50V

4.7µF

C

ADP1972

R

Figure 17. Recommended Filter Configuration for

Input Voltages Greater than 50 V

Rev. B | Page 10 of 18