Data Sheet

ADP1972

PCB LAYOUT GUIDELINES

For high efficiency, good regulation, and stability, a well

designed PCB layout is required.

Use the following guidelines when designing the PCB (see

Figure 16 for the block diagram and Figure 2 for the pin

configuration).

•

Keep the low effective series resistance (ESR) input supply

GND pins to minimize noise being injected into the device

from board parasitic inductance.

•

as close as possible to the VREG and GND pins to

minimize noise being injected into the device from board

parasitic inductance.

•

Place the components for the SCFG, FREQ, DMAX, and SS

pins close to the corresponding pins. Tie these components

collectively to an AGND plane that makes a Kelvin connection

to the GND pin.

•

Keep the trace from the COMP pin to the accompanying

device (for example, AD8450) as short as possible. Avoid

routing this trace near switching signals and shield the

trace if possible.

•

Place any trace or components for the SYNC pin away from

sensitive analog nodes. When using an external pull-up, it is

best to use a local 0.1 µF bypass capacitor from the supply

of the pull-up resistor to GND.

•

Keep the traces from the DH and DL pins to the external

components as short as possible to minimize parasitic

inductance and capacitance, which affect the control

signal. The DH and DL pins are switching nodes; do not

route them near any sensitive analog circuitry.

•

Keep high current traces as short and as wide as possible.

•

Connect the ground connection of the ADP1972 directly

•

•

Use a Kelvin connection shown in Figure 24 and Figure 25

from the following:

o

o

o

Extra resistance due to PCB routing introduces a voltage

This voltage difference must not exceed ±0.3 V.

•

When building a system with a master and multiple slave

devices, the capacitance of the trace attached to the SYNC

pin must be minimized.

o

For small systems with only a few slave devices, a

resistor connected in series between the master SYNC

signal and the slave SYNC input pins limits the

capacitance of the trace and reduces the fast ground

currents that can inject noise into the master device.

o

For larger applications, the series resistance is not

enough to isolate the master SYNC clock. In larger

systems, use an external buffer to reduce the

capacitance of the trace. The external buffer has the

drive capability to support a large number of slave

devices.

GND

CL

20kΩ

NMOS

POWER

FET

SOURCE

GROUND

BUS

CL

GND

Rev. B | Page 17 of 18