ADP5041ACPZ-1-R7 datasheet(26/40 Pages) AD

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ADP5041

Data Sheet

Rev. B | Page 26 of 40

THEORY OF OPERATION

PWM/

PSM

CONTROL

BUCK1

DRIVER

AND

ANTISHOOT

THROUGH

RESET

GENERATOR

DEBOUNCE

VDDA

PSM

COMP

LOW

CURRENT

ILIMIT

ADP5041

VOUT1 FB1

VTHR

ENWD

VIN1

AVIN

PGND

EN1

ENBK

ENLDO1

ENLDO2

MODE

EN2

EN3

SEL

OPMODE_FUSES

VIN2

FB2 AGND VOUT2 VIN3

ENLDO1

600Ω

ENBK

ENLDO2

600Ω

VDDA

52kΩ

WDI

VOUT3

FB3

OSCILLATOR

THERMAL

SHUTDOWN

VREF

WATCHDOG

DETECTOR

nRSTO

VDDA

PWM

COMP

GM ERROR

AMP

85Ω

SOFT START

SYSTEM

UNDERVOLTAGE

LOCK OUT

ENABLE

AND MODE

CONTROL

LDO1

CONTROL

LDO2

CONTROL

Figure 101. Functional Block Diagram

POWER MANAGEMENT UNIT

The ADP5041 is a micro power management unit (micro PMU)

combing one step-down (buck) dc-to-dc regulator, two LDO

linear regulators, and a supervisory circuit, with watchdog, for

processor control. The high switching frequency and tiny 20-pin

LFCSP package allow for a small power management solution.

The regulators are activated by a logic level high applied to the

respective EN pin. The EN1 pin controls the buck regulator, the

EN2 pin controls LDO1, and the EN3 pin controls LDO2.

Other features available on this device are the MODE pin to

control the buck switching operation and a push-button reset

input.

The regulator output voltages and the reset threshold are set

through external resistor dividers.

When a regulator is turned on, the output voltage ramp is

controlled through a soft start circuit to avoid a large inrush

current due to the discharged output capacitors.

The buck regulator can operate in forced PWM mode if the

MODE pin is at a logic high level. In forced PWM mode, the

switching frequency of the buck is always constant and does not

change with the load current. If the MODE pin is at a logic low

level, the switching regulator operates in auto PWM/PSM mode.

In this mode, the regulator operates at fixed PWM frequency

when the load current is above the power save current threshold.

When the load current falls below the power saving current

threshold, the regulator enters power saving mode, where the

switching occurs in bursts. The burst repetition rate is a

function of the current load and the output capacitor value.

This operating mode reduces the switching and quiescent

current losses.

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ADP5041ACPZ-1-R7 数据表(PDF) 26 Page - Analog Devices

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