ADP5041ACPZ-1-R7 datasheet(35/40 Pages) AD

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Data Sheet

ADP5041

Rev. B | Page 35 of 40

The inductor losses are estimated (without core losses) by

RMS

OUT1

DCR





)

(

(4)

where:

DCRL is the inductor series resistance.

IOUT1(RMS) is the rms load current of the buck regulator.

/12

)

(

OUT1

RMS

OUT1





(5)

where r is the normalized inductor ripple current.

r ≈ VOUT1 × (1-D)/(IOUT1 × L × fSW)

(6)

where:

L is inductance.

fSW is switching frequency.

D is duty cycle.

D = VOUT1/VIN1

(7)

The ADP5041 buck regulator power dissipation, PDBUCK, includes

the power switch conductive losses, the switch losses, and the

transition losses of each channel. There are other sources of

loss, but these are generally less significant at high output load

currents, where the thermal limit of the application is. Equation 8

shows the calculation made to estimate the power dissipation in

the buck regulator.

PDBUCK = PCOND + PSW + PTRAN

(8)

The power switch conductive losses are due to the output current,

IOUT1, flowing through the PMOSFET and the NMOSFET power

switches that have internal resistance, RDSON-P and RDSON-N. The

amount of conductive power loss is found by:

PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT12

(9)

For the ADP5041, at 125°C junction temperature and VIN1 =

3.6 V, RDSON-P is approximately 0.2 Ω, and RDSON-N is approximately

0.16 Ω. At VIN1 = 2.3 V, these values change to 0.31 Ω and

0.21 Ω respectively, and at VIN1 = 5.5 V, the values are 0.16 Ω

and 0.14 Ω, respectively.

Switching losses are associated with the current drawn by the

driver to turn on and turn off the power devices at the switching

frequency. The amount of switching power loss is given by:

PSW = (CGATE-P + CGATE-N) × VIN12 × fSW

(10)

where:

CGATE-P is the PMOSFET gate capacitance.

CGATE-N is the NMOSFET gate capacitance.

For the ADP5041, the total of (CGATE-P + CGATE-N) is

approximately 150 pF.

The transition losses occur because the PMOSFET cannot be

turned on or off instantaneously, and the SW node takes some

time to slew from near ground to near VOUT1 (and from VOUT1 to

ground). The amount of transition loss is calculated by:

PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW

(11)

where tRISE and tFALL are the rise time and the fall time of the

switching node, SW. For the ADP5041, the rise and fall times of

SW are in the order of 5 ns.

If the preceding equations and parameters are used for

estimating the converter efficiency, it must be noted that the

equations do not describe all of the converter losses, and the

parameter values given are typical numbers. The converter

performance also depends on the choice of passive components

and board layout; therefore, a sufficient safety margin should be

included in the estimate.

LDO Regulator Power Dissipation

The power loss of a LDO regulator is given by:

PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND)

(12)

where:

ILOAD is the load current of the LDO regulator.

VIN and VOUT are input and output voltages of the LDO,

respectively.

IGND is the ground current of the LDO regulator.

Power dissipation due to the ground current is small and it

can be ignored.

The total power dissipation in the ADP5041 simplifies to:

PD = {[PDBUCK + PDLDO1 + PDLDO2]}

(13)

Junction Temperature

In cases where the board temperature, TA, is known, the

thermal resistance parameter, θJA, can be used to estimate the

junction temperature rise. TJ is calculated from TA and PD using

the formula

TJ = TA + (PD × θJA)

(14)

The typical θJA value for the 20-lead, 4 mm × 4 mm LFCSP is

38°C/W (see Table 7). A very important factor to consider is

that θJA is based on a 4-layer, 4 inch × 3 inch, 2.5 oz copper, as

per JEDEC standard, and real applications may use different

sizes and layers. To remove heat from the device, it is important

to maximize the use of copper. Copper exposed to air dissipates

heat better than copper used in the inner layers. The exposed

pad (EP) should be connected to the ground plane with several

vias as shown in Figure 114.

If the case temperature can be measured, the junction temperature

is calculated by

TJ = TC + (PD × θJC)

(15)

where:

TC is the case temperature.

θJC is the junction-to-case thermal resistance provided in

Table 7.

When designing an application for a particular ambient

temperature range, calculate the expected ADP5041 power

dissipation (PD) due to the losses of all channels by using

Equation 8 to Equation 13. From this power calculation, the

junction temperature, TJ, can be estimated using Equation 14.

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