Micro PMU with 1.2 A Buck, Two 300 mA LDOs,

Supervisory, Watchdog, and Manual Reset

Data Sheet

ADP5041

Rev. B

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FEATURES

Input voltage range: 2.3 V to 5.5 V

One 1.2 A buck regulator

Two 300 mA LDOs

20-lead, 4 mm × 4 mm LFCSP package

Overcurrent and thermal protection

Soft start

Undervoltage lockout

Open-drain processor reset with externally adjustable

threshold monitoring

Manual reset input

Watchdog refresh input

Buck key specifications

Output voltage range: 0.8 V to 3.8 V

Current mode topology for excellent transient response

3 MHz operating frequency

Peak efficiency up to 96%

Uses tiny multilayer inductors and capacitors

Mode pin selects forced PWM or auto PWM/PSM mode

100% duty cycle low dropout mode

LDOs key specifications

Output voltage range: 0.8 V to 5.2 V

Low input supply voltage from 1.7 V to 5.5 V

Stable with 2.2 μF ceramic output capacitors

High PSRR

Low output noise

Low dropout voltage

−40°C to +125°C junction temperature range

FUNCTIONAL BLOCK DIAGRAM

SW

EN_BK

FB2

R4

R4

R5

R3

FB3

R3

R7

C5

2.2µF

C6

2.2µF

VOUT2

AVIN

VBIAS

VBIAS

VOUT1

FB1

L1

1µH

R1

R2

5.5V

C1

4.7µF

SUPERVISOR

µP

nRSTO

WDI

VTHR

MR

TO 5.5V

VIN1

ON

OFF

ON

OFF

ON

OFF

EN1

VIN2

C2

1µF

C3

1µF

EN2

EN3

VIN3

TO 5.5V

EN_LDO2

LDO2

(ANALOG)

BUCK

AGND

1.2A

C6

10µF

PGND

FPWM

PSM/PWM

MODE

300mA

300mA

VOUT3

LDO1

(DIGITAL)

EN_LDO1

Figure 1.

GENERAL DESCRIPTION

The ADP5041 combines one high performance buck regulator

and two low dropout (LDO) regulators in a small 20-lead

LFCSP to meet demanding performance and board space

requirements.

The high switching frequency of the buck regulator enables

use of tiny multilayer external components and minimizes

board space.

When the MODE pin is set to logic high, the buck regulator

operates in forced PWM mode. When the MODE pin is set to

logic low, the buck regulator operates in PWM mode when the

load is around the nominal value. When the load current falls

below a predefined threshold, the regulator operates in power

save mode (PSM), improving the light load efficiency. The low

quiescent current, low dropout voltage, and wide input voltage

range of the ADP5041 LDOs extend the battery life of portable

devices. The ADP5041 LDOs maintain a power supply rejection

greater than 60 dB for frequencies as high as 10 kHz while

operating with a low headroom voltage.

Each regulator in the ADP5041 is activated by a high level on

the respective enable pin. The output voltages of the regulators

and the reset threshold are programmed through external resistor

dividers to address a variety of applications. The ADP5041

contains supervisory circuits that monitor power supply voltage

levels and code execution integrity in microprocessor-based

systems. They also provide power-on reset signals. An on-chip

watchdog timer can reset the microprocessor if it fails to strobe

within a preset timeout period.