ADP5041ACPZ-1-R7 datasheet(33/40 Pages) AD

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Data Sheet

ADP5041

Rev. B | Page 33 of 40

Table 13. Suggested 1.0 μF Capacitors

Vendor

Type

Model

Case Size

Voltage

Rating (V)

Murata

X5R

GRM155B30J105K

0402

6.3

TDK

X5R

C1005JB0J105KT

0402

6.3

Panasonic

X5R

ECJ0EB0J105K

0402

6.3

Taiyo

Yuden

X5R

LMK105BJ105MV-F

0402

10.0

Input and Output Capacitor Properties

Use any good quality ceramic capacitor with the ADP5041 as

long as it meets the minimum capacitance and maximum ESR

requirements. Ceramic capacitors are manufactured with a variety

of dielectrics, each with a different behavior over temperature

and applied voltage. Capacitors must have a dielectric adequate

to ensure the minimum capacitance over the necessary tempe-

rature range and dc bias conditions. X5R or X7R dielectrics

with a voltage rating of 6.3 V or 10 V are recommended for best

performance. Y5V and Z5U dielectrics are not recommended

for use with any LDO because of their poor temperature and dc

bias characteristics.

Figure 110 depicts the capacitance vs. dc voltage bias characteristic

of a 0402 1 μF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or higher voltage

rating exhibits better stability. The temperature variation of the

X5R dielectric is about ±15% over the −40°C to +85°C tempera-

ture range and is not a function of package or voltage rating.

1.2

1.0

0.8

0.6

0.4

0.2

123

DC BIAS VOLTAGE (V)

Figure 110. Capacitance vs. Voltage Characteristic

Use the following equation to determine the worst-case capa-

citance, accounting for capacitor variation over temperature,

component tolerance, and voltage.

CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)

where:

CBIAS is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient

(TEMPCO) over −40°C to +85°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10%, and CBIAS is 0.94 μF at 1.8 V, as shown in Figure 110.

Substituting these values into the following equation yields:

CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.72 μF

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over

temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP5041, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

SUPERVISORY SECTION

Threshold Setting Resistors

Referring to Figure 105, the maximum value of R2 is not to

exceed 200 kΩ.

Watchdog Input Current

To minimize watchdog input current (and minimize overall

power consumption), leave WDI low for the majority of the

watchdog timeout period. When driven high, WDI can draw

as much as 25 μA. Pulsing WDI low-to-high-to-low at a low

duty cycle reduces the effect of the large input current. When

WDI is unconnected, a window comparator disconnects the

watchdog timer from the reset output circuitry so that reset is

not asserted when the watchdog timer times out.

Negative-Going Transients at the Monitored Rail

To avoid unnecessary resets caused by fast power supply transients,

the ADP5041 is equipped with glitch rejection circuitry. The typical

performance characteristic in Figure 111 plots the monitored

rail voltage, VTH, transient duration vs. the transient magnitude.

The curve shows combinations of transient magnitude and

duration for which a reset is not generated. In this example,

with the 3.00 V threshold, a transient that goes 100 mV below

the threshold and lasts 8 μs typically does not cause a reset, but

if the transient is any larger in magnitude or duration, a reset is

generated. In this example, the reset threshold programming

resistor values were R2 = 200 kΩ, R1 = 1 MΩ (see Figure 105).

900

800

700

600

500

400

300

200

100

0.1

100

COMPARATOR OVERDRIVE (% OF VTH)

Figure 111. Maximum VTH Transient Duration vs. Reset

Threshold Overdrive

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