LM5035 datasheet(19/28 Pages) NSC

19 / 28 page

Applications Information (Continued)

If the current sense resistor method is used, the over-current

condition will only be sensed while LO is driving the low-side

MOSFET. Over-current while HO is driving the high-side

MOSFET will not be detected. In this configuration, it will

take 4 times as long for continuous cycle-by-cycle current

limiting to initiate a restart event since each over-current

event during LO enables the 22µA RES pin current source

for one oscillator period, and then the lack of an over-current

event during HO enables the 12µA RES pin current sink for

one oscillator period. The time average of this toggling is

equivalent to a continuous 5µA current source into the RES

capacitor, increasing the delay by a factor of four. The value

of the RES capacitor can be reduced to decrease the time

before restart cycle is initiated.

HO, HB, HS and LO

Attention must be given to the PC board layout for the

low-side driver and the floating high-side driver pins HO, HB

and HS. A low ESR/ESL capacitor (such as a ceramic sur-

face mount capacitor) should be connected close to the

LM5035, between HB and HS to provide high peak currents

during turn-on of the high-side MOSFET. The capacitor

should be large enough to supply the MOSFET gate charge

(Qg) without discharging to the point where the drop in gate

voltage affects the MOSFET R

DS(ON). A value ten to twenty

times Qg is recommended.

The diode (D

BOOST) that charges CBOOST from VCC when

the low-side MOSFET is conducting should be capable of

withstanding the full converter input voltage range. When the

high-side MOSFET is conducting, the reverse voltage at the

diode is approximately the same as the MOSFET drain

voltage because the high-side driver is boosted up to the

converter input voltage by the HS pin, and the high side

MOSFET gate is driven to the HS voltage plus VCC. Since

the anode of D

BOOST is connected to VCC, the reverse

potential across the diode is equal to the input voltage minus

the VCC voltage. D

BOOST average current is less than 20mA

in most applications, so a low current ultra-fast recovery

diode is recommended to limit the loss due to diode junction

capacitance. Schottky diodes are also a viable option, par-

ticularly for lower input voltage applications, but attention

must be paid to leakage currents at high temperatures.

The internal gate drivers need a very low impedance path to

the respective decoupling capacitors; the VCC cap for the

LO driver and C

BOOST for the HO driver. These connections

should be as short as possible to reduce inductance and as

wide as possible to reduce resistance. The loop area, de-

fined by the gate connection and its respective return path,

should be minimized.

The high-side gate driver can also be used with HS con-

nected to PGND for applications other than a half bridge

converter (e.g. Push-Pull). The HB pin is then connected to

VCC, or any supply greater than the high-side driver under-

voltage lockout (approximately 6.5V). In addition, the high-

side driver can be configured for high voltage offline appli-

cations where the high-side MOSFET gate is driven via a

gate drive transformer.

PROGRAMMABLE DELAY (DLY)

The R

DLY resistor programs the delays between the SR1 and

SR2 signals and the HO and LO driver outputs. Figure 5

shows the relationship between these outputs. The DLY pin

is nominally set at 2.5V and the current is sensed through

DLY to ground. This current is used to adjust the amount of

deadtime before the HO and LO pulse (T1) and after the HO

and LO pulse (T2). Typically R

DLY is in the range of 10k

Ω to

100k

Ω. The deadtime periods can be calculated using the

following formulae:

T1=[R

DLY x 2.8ps] + 20ns

T2=[R

DLY x 1.35ps] + 6ns

T1 and T2 can be set to minimum by not connecting a

resistor to DLY, connecting a resistor greater than 300k

Ω

from DLY to ground, or connecting DLY to the REF pin. This

may cause lower than optimal system efficiency if the delays

through the SR signal transformer network, the secondary

gate drivers and the SR MOSFETs are greater than the

delay to turn on the HO or LO MOSFETs. Should an SR

MOSFET remain on while the opposing primary MOSFET is

supplying power through the power transformer, the second-

ary winding will experience a momentary short circuit, caus-

ing a significant power loss to occur.

When choosing the R

DLY value, worst case propagation

delays and component tolerances should be considered to

assure that there is never a time where both SR MOSFETs

are enabled AND one of the primary side MOSFETs is

enabled. The time period T1 should be set so that the SR

MOSFET has turned off before the primary MOSFET is

enabled. Conversely, T1 and T2 should be kept as low as

tolerances allow to optimize efficiency. The SR body diode

conducts during the time between the SR MOSFET turns off

and the power transformer begins supplying energy. Power

losses increase when this happens since the body diode

voltage drop is many times higher than the MOSFET chan-

nel voltage drop. The interval of body diode conduction can

be observed with an oscilloscope as a negative 0.7V to 1.5V

pulse at the SR MOSFET drain.

UVLO AND OVP VOLTAGE DIVIDER SELECTION FOR

R1, R2, AND R3

Two dedicated comparators connected to the UVLO and

OVP pins are used to detect under-voltage and over-voltage

conditions. The threshold value of these comparators, V

UVLO

and V

OVP, is 1.25V (typical). The two functions can be

programmed independently with two voltage dividers from

VIN to AGND as shown in Figure 10 and Figure 11, or with a

three-resistor divider as shown in Figure 12. Independent

UVLO and OVP pins provide greater flexibility for the user to

select the operational voltage range of the system. Hyster-

esis is accomplished by 23µA current sources (I

UVLO and

OVP), which are switched on or off into the sense pin resistor

dividers as the comparators change state.

When the UVLO pin voltage is below 0.4V, the controller is in

a low current shutdown mode. For a UVLO pin voltage

greater than 0.4V but less than 1.25V the controller is in

standby mode. Once the UVLO pin voltage is greater than

1.25V, the controller is fully enabled. Two external resistors

can be used to program the minimum operational voltage for

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