LM5035 datasheet(3/28 Pages) NSC

3 / 28 page

Ordering Information

Order Number

Package Type

NSC Package Drawing

Supplied As

LM5035MH

TSSOP-20EP

MXA20A

73 Units per Rail

LM5035MHX

TSSOP-20EP

MXA20A

2500 Units on Tape and Reel

LM5035SQ

LLP-24

SQA24B

Available Soon

LM5035SQX

LLP-24

SQA24B

Available Soon

Pin Descriptions

TSSOP

LLP

Name

Description

Application Information

RAMP

Modulator ramp signal

An external RC circuit from VIN sets the ramp slope. This pin

is discharged at the conclusion of every cycle by an internal

FET. Discharge is initiated by either the internal clock or the

Volt

• Second clamp comparator.

UVLO

Line Under-Voltage Lockout

An external voltage divider from the power source sets the

shutdown and standby comparator levels. When UVLO

reaches the 0.4V threshold the VCC and REF regulators are

enabled. When UVLO reaches the 1.25V threshold, the SS pin

is released and the device enters the active mode. Hysteresis

is set by an internal current sink that pulls 23µA from the

external resistor divider.

OVP

Line Over-Voltage Protection

An external voltage divider from the power source sets the

shutdown levels. The threshold is 1.25V. Hysteresis is set by

an internal current source that sources 23µA into the external

resistor divider.

COMP

Input to the Pulse Width

Modulator

An external opto-coupler connected to the COMP pin sources

current into an internal NPN current mirror. The PWM duty

cycle is maximum with zero input current, while 1mA reduces

the duty cycle to zero. The current mirror improves the

frequency response by reducing the AC voltage across the

opto-coupler detector.

Oscillator Frequency Control and

Sync Clock Input.

Normally biased at 2V. An external resistor connected between

RT and AGND sets the internal oscillator frequency. The

internal oscillator can be synchronized to an external clock with

a frequency higher than the free running frequency set by the

RT resistor.

AGND

Analog Ground

Connect directly to Power Ground.

Current Sense input for current

limit

If CS exceeds 0.25V the output pulse will be terminated,

entering cycle-by-cycle current limit. An internal switch holds

CS low for 50ns after HO or LO switches high to blank leading

edge transients.

Soft-start Input

An internal 55 µA current source charges an external capacitor

to set the soft-start rate. During a current limit restart

sequence, the internal current source is reduced to 1.2µA to

increase the delay before retry.

DLY

Timing programming pin for the

LO and HO to SR1 and SR2

outputs.

An external resistor to ground sets the timing for the

non-overlap time of HO to SR1 and LO to SR2.

LM5035 数据表(PDF) 3 Page - National Semiconductor (TI)

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