LM5035 datasheet(15/28 Pages) NSC

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Feed-Forward Ramp and Volt

•

Second Clamp (Continued)

tude exceeds the 2.5V threshold of the Volt

• Second Clamp

comparator, the on-time is terminated. The C

FF ramp capaci-

tor is discharged by an internal 32

Ω discharge MOSFET

controlled by the V

•S Clamp comparator. If the RAMP signal

does not exceed 2.5V before the end of the clock period,

then the internal clock will enable the discharge MOSFET to

reset capacitor C

FF.

By proper selection of R

FF and CFF values, the maximum

on-time of HO and LO can be set to the desired duration.

The on-time set by the Volt

• Second Clamp varies inversely

to the line voltage because the RAMP capacitor is charged

by a resistor (R

FF) connected to VIN while the threshold of

the clamp is a fixed voltage (2.5V). An example will illustrate

the use of the Volt

• Second Clamp comparator to achieve a

50% duty cycle limit at 200kHz with a 48V line input. A 50%

duty cycle at a 200kHz requires a 2.5µs on-time. To achieve

this maximum on-time clamp level:

The recommended capacitor value range for C

FF is 100pF to

1000pF. 470pF is a standard value that can be paired with an

110k

Ω to approximate the desired 51.4µs time constant. If

load transient response is slowed by the 10% margin, the

FF value can be increased. The system signal-to-noise will

be slightly decreased by increasing R

FF xCFF.

Oscillator, Sync Capability

The LM5035 oscillator frequency is set by a single external

resistor connected between the RT and AGND pins. To set a

desired oscillator frequency, the necessary RT resistor is

calculated from:

For example, if the desired oscillator frequency is 400kHz

(HO and LO each switching at 200kHz) a 15k

Ω resistor

would be the nearest standard one percent value.

Each output (HO, LO, SR1 and SR2) switches at half the

oscillator frequency. The voltage at the RT pin is internally

regulated to a nominal 2V. The RT resistor should be located

as close as possible to the IC, and connected directly to the

pins (RT and AGND). The tolerance of the external resistor,

and the frequency tolerance indicated in the Electrical Char-

acteristics, must be taken into account when determining the

worst case frequency range.

The LM5035 can be synchronized to an external clock by

applying a narrow pulse to the RT pin. The external clock

must be at least 10% higher than the free-running oscillator

frequency set by the RT resistor. If the external clock fre-

quency is less than the RT resistor programmed frequency,

the LM5035 will ignore the synchronizing pulses. The syn-

chronization pulse width at the RT pin must be a minimum of

15 ns wide. The clock signal should be coupled into the RT

pin through a 100pF capacitor or a value small enough to

ensure the pulse width at RT is less than 60% of the clock

period under all conditions. When the synchronizing pulse

transitions low-to-high (rising edge), the voltage at the RT pin

must be driven to exceed 3.2V volts from its nominal 2 VDC

level. During the clock signal’s low time, the voltage at the

RT pin will be clamped at 2 VDC by an internal regulator. The

output impedance of the RT regulator is approximately

100

Ω. The RT resistor is always required, whether the oscil-

lator is free running or externally synchronized.

Gate Driver Outputs (HO & LO)

The LM5035 provides two alternating gate driver outputs,

the floating high side gate driver HO and the ground refer-

enced low side driver LO. Each driver is capable of sourcing

1.25A and sinking 2A peak. The HO and LO outputs operate

in an alternating manner, at one-half the internal oscillator

frequency. The LO driver is powered directly by the VCC

regulator. The HO gate driver is powered from a bootstrap

capacitor connected between HB and HS. An external diode

connected between VCC (anode pin) and HB (cathode pin)

provides the high side gate driver power by charging the

bootstrap capacitor from VCC when the switch node (HS

pin) is low. When the high side MOSFET is turned on, HB

rises to a peak voltage equal to V

VCC +VHS where VHS is the

switch node voltage.

The HB and VCC capacitors should be placed close to the

pins of the LM5035 to minimize voltage transients due to

parasitic inductances since the peak current sourced to the

MOSFET gates can exceed 1.25A. The recommended value

of the HB capacitor is 0.01µF or greater. A low ESR / ESL

capacitor, such as a surface mount ceramic, should be used

to prevent voltage droop during the HO transitions.

The maximum duty cycle for each output is limited to slightly

less than 50% due to the internally fixed deadtime. If the

COMP pin is open circuit, the outputs will operate at maxi-

mum duty cycle. The typical deadtime in this condition is

70ns which does not vary with operating frequency. The

maximum duty cycle for each output can be calculated with

the following equation:

where T

S is the period of one complete cycle for both HO

and LO outputs, and T

D is the deadtime. For example, if the

oscillator frequency is 200 kHz, each output will cycle at 100

kHz (T

S = 10µs). Using the nominal deadtime of 70ns, the

maximum duty cycle at this frequency is calculated to be

49.3%.

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