LM5035 datasheet(14/28 Pages) NSC

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Overload Protection Timer (Continued)

Soft-Start

The soft-start circuit allows the regulator to gradually reach a

steady state operating point, thereby reducing start-up

stresses and current surges. When bias is supplied to the

LM5035, the SS pin capacitor is discharged by an internal

MOSFET. When the UVLO, VCC and REF pins reach their

operating thresholds, the SS capacitor is released and

charged with a 55µA current source. The PWM comparator

control voltage is clamped to the SS pin voltage by an

internal amplifier. When the PWM comparator input reaches

1V, output pulses commence with slowly increasing duty

cycle. The voltage at the SS pin eventually increases to 5V,

while the voltage at the PWM comparator increases to the

value required for regulation as determined by the voltage

feedback loop.

One method to shutdown the regulator is to ground the SS

pin. This forces the internal PWM control signal to ground,

reducing the output duty cycle quickly to zero. Releasing the

SS pin begins a soft-start cycle and normal operation re-

sumes. A second shutdown method is discussed in the

UVLO section.

Soft-Stop

If the UVLO pin voltage falls below the 1.25V standby thresh-

old but above the 0.4V shutdown threshold, the 55µA SS pin

source current is disabled and a 55µA sink current dis-

charges the soft-start capacitor. As SS voltage falls and

clamps the PWM comparator input, the PWM duty cycle will

gradually fall to zero. The soft-stop feature produces a

gradual reduction of the power converter output voltage. This

soft-stop method of turning off the converter reduces energy

in the output capacitor before control of the main and syn-

chronous rectification MOSFETs is disabled. The PWM

pulses may cease before the SS voltage reduces the duty

cycle if the VCC or REF voltage drops below the respective

under-voltage thresholds during the soft-stop process.

PWM Comparator

The pulse width modulation (PWM) comparator compares

the voltage ramp signal at the RAMP pin to the loop error

signal. This comparator is optimized for speed in order to

achieve minimum controllable duty cycles. The loop error

signal is received from the external feedback and isolation

circuit is in the form of a control current into the COMP pin.

The COMP pin current is internally mirrored by a matched

pair of NPN transistors which sink current through a 5k

Ω

resistor connected to the 5V reference. The resulting control

voltage passes through a 1V level shift before being applied

to the PWM comparator.

An opto-coupler detector can be connected between the

REF pin and the COMP pin. Because the COMP pin is

controlled by a current input, the potential difference across

the optocoupler detector is nearly constant. The bandwidth

limiting phase delay which is normally introduced by the

significant capacitance of the opto-coupler is thereby greatly

reduced. Higher loop bandwidths can be realized since the

bandwidth-limiting pole associated with the opto-coupler is

now at a much higher frequency. The PWM comparator

polarity is configured such that with no current into the

COMP pin, the controller produces the maximum duty cycle

at the main gate driver outputs, HO and LO.

Feed-Forward Ramp and Volt

•

Second Clamp

An external resistor (R

FF) and capacitor (CFF) connected to

VIN, AGND, and the RAMP pin are required to create the

PWM ramp signal. The slope of the signal at RAMP will vary

in proportion to the input line voltage. This varying slope

provides line feed-forward information necessary to improve

line transient response with voltage mode control. The

RAMP signal is compared to the error signal by the pulse

width modulator comparator to control the duty cycle of the

HO and LO outputs. With a constant error signal, the on-time

ON) varies inversely with the input voltage (VIN) to stabilize

the Volt

• Second product of the transformer primary signal.

The power path gain of conventional voltage-mode pulse

width modulators (oscillator generated ramp) varies directly

with input voltage. The use of a line generated ramp (input

voltage feed-forward) nearly eliminates this gain variation.

As a result, the feedback loop is only required to make very

small corrections for large changes in input voltage.

In addition to the PWM comparator, a Volt

• Second Clamp

comparator also monitors the RAMP pin. If the ramp ampli-

20177517

FIGURE 4. Optocoupler to COMP Interface

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