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2022 Microchip Technology Inc. and its subsidiaries

DS00002514B-page 19

USB4715

5.1

Boot Sequence

5.1.1

STANDBY MODE

If the

RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maxi-

mum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream

ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no

states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order

to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode

and must be re-initialized after

RESET_N is negated high.

5.1.2

SPI INITIALIZATION STAGE (SPI_INIT)

The first stage, the initialization stage, occurs on the deassertion of

RESET_N. In this stage, the internal logic is reset,

the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal

firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid

signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the SPI

Firmware/external SPI ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If

a valid signature is not found, then execution continues from internal ROM (CFG_ROM stage).

When using an external SPI ROM, a minimum of 2.2 Mbit is required, and 60 MHz or faster SPI ROM must be used.

Both 1- and 2-bit SPI ROM are supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0

and mode 3 SPI flashes are supported.

If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_ROM stage).

5.1.3

CONFIGURATION FROM INTERNAL ROM STAGE (CFG_ROM)

In this stage, the internal firmware loads the default values from the internal ROM. Most of the hub configuration regis-

ters, USB descriptors, electrical settings, etc. will be initialized in this state even when running from SPI.

5.1.4

CONFIGURATION STRAP READ STAGE (CFG_STRAP)

In this stage, the firmware reads the following configuration straps to override the default values:

• CONFIG_STRAP_[2:1]

•

PRT_DIS_P[4:1]

•

PRT_DIS_M[4:1]

•

CFG_NON_REM

•

CFG_BC_EN

If the

CONFIG_STRAP_[2:1] pins are set to Configuration 5, the device will move to the SMBUS_CHECK stage, other-

wise it move to the CFG_OTP stage. Refer to Section 3.3, "Configuration Straps and Programmable Functions" for infor-

mation on usage of the various device configuration straps.

5.1.5

SMBUS CHECK STAGE (SMBUS_CHECK)

Based on the

PROG_FUNC[8:1] configuration selected (refer to Section 3.3.4, "PROG_FUNC[8:1] Configuration (CON-

FIG_STRAP_[2:1])"), the firmware will check for the presence of external pull up resistors on the SMBus slave program-

mable function pins. If 10K pull-ups are detected on both pins, the device will be configured as an SMBus slave, and

the next state will be CFG_SOC. If a pull-up is not detected in either of the pins, the next state is CFG_OTP.

5.1.6

SOC CONFIGURATION STAGE (CFG_SOC)

In this stage, the SOC can modify any of the default configuration settings specified in the integrated ROM, such as USB

device descriptors, port electrical settings, and control features such as downstream battery charging.

external SMBus master writes to register 0xFF, to end the configuration in legacy mode. In non-legacy mode, the SMBus

command USB_ATTACH (opcode 0xAA55) or USB_ATTACH_WITH_SMBUS (opcode 0xAA56) will finish the configu-

ration.

5.1.7

OTP CONFIGURATION STAGE (CFG_OTP)

Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The

default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is pro-

grammed.