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2022 Microchip Technology Inc. and its subsidiaries

DS00002514B-page 29

USB4715

8.8.2.3

Port Power Control with Single Poly Fuse and Multiple Loads

Many customers use a single poly fuse to power all their devices. For the ganged situation, all power control pins must

be tied together.

8.9

Resets

The device includes the following chip-level reset sources:

• Power-On Reset (POR)

• External Chip Reset (RESET_N)

• USB Bus Reset

8.9.1

POWER-ON RESET (POR)

A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the

device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.2, "Power-On

and Configuration Strap Timing," on page 34.

8.9.2

EXTERNAL CHIP RESET (

RESET_N)

A valid hardware reset is defined as assertion of

RESET_N, after all power supplies are within operating range, per the

specifications in Section 9.6.3, "Reset and Configuration Strap Timing," on page 35. While reset is asserted, the device

(and its associated external circuitry) enters Standby Mode and consumes minimal current.

Assertion of

RESET_N causes the following:

1. The PHY is disabled and the differential pairs will be in a high-impedance state.

2. All transactions immediately terminate; no states are saved.

3. All internal registers return to the default state.

4. The external crystal oscillator is halted.

5. The PLL is halted.

FIGURE 8-4:

PORT POWER CONTROL WITH GANGED CONTROL WITH POLY FUSE

Note:

All power supplies must have reached the operating levels mandated in Section 9.2, "Operating Condi-

tions**," on page 31, prior to (or coincident with) the assertion of

RESET_N.

Pull-Up Enable

USB

Device

Poly Fuse

5V

Pull-Up Enable

Pull-Up Enable

50k

50k

50k

PRTPWR

OCS

USB

Device

USB

Device

PRT_CTLx

PRT_CTLy

PRT_CTLz