USB4715 datasheet(12/47 Pages) MICROCHIP

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USB4715

DS00002514B-page 12



2022 Microchip Technology Inc. and its subsidiaries

Note 3-1

Configuration strap values are latched on Power-On Reset (POR) and the rising edge of

RESET_N

(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that

function as configuration straps must be augmented with an external resistor when connected to a

load. For additional information, refer to Section 3.3, "Configuration Straps and Programmable

Functions".

Port 4-1 D-

Disable

Configuration

Strap

PRT_DIS_M[4:1]

Port 4-1 D- Disable configuration strap.

These configuration straps are used in conjunction with

the corresponding

PRT_DIS_P[4:1] straps to disable the

related port (5-1). See Note 3-1.

Both USB data pins for the corresponding port must be

tied to 3.3V to disable the associated downstream port.

Non-Removable

Ports

Configuration

Strap

CFG_NON_REM

Non-Removable Ports Configuration Strap.

This configuration strap controls the number of reported

non-removable ports. See Note 3-1.

Battery Charging

Configuration

Strap

CFG_BC_EN

Battery Charging Configuration Strap.

This configuration strap controls the number of BC 1.2

enabled downstream ports. See Note 3-1.

Power/Ground

+3.3V I/O Power

Supply Input

VDDIO33

+3.3V I/O power supply input.

+3.3V Analog

Power Supply

Input

VDDPLLREF33

+3.3V master bias / PLL regulator supply input.

+1.2V Core

Power Supply

Output

VDDCR12

+1.2V digital core power supply output.

Note:

This signal requires connection of a 1uF low-

ESR capacitor to ground.

Ground

VSS

Ground pins.

TABLE 3-2:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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