STPM10 datasheet(18/47 Pages) STMICROELECTRONICS

18 / 47 page

Theory of operation

STPM10

18/47

DocID17728 Rev 5

Table 7: Configuration of current sensors

Primary

Secondary

Configuration bits

Gain

Sensor

Gain

Sensor

PST

TMP

Disabled

Shunt

Disabled

Shunt

If the device is used in configuration PST = 1, TMP = 1 (primary channel with CT,

secondary channel with Shunt), the shunt Ks must always be equal to one fourth

of the current transformer Ks.

Both the voltage and current channels implement an active offset correction architecture

which provides the benefit of avoiding any offset compensation. The analog voltage and

current signals are processed by

the ΣΔ analog-to-digital converters, which feed the

hardwired DSP. The DSP implements an automatic digital offset cancellation that makes it

possible to avoid any manual offset calibration on the analog inputs.

7.3

ΣΔ A/D converters

Analog-to-digital conversion in the STPM10 is carried out using two first-

order ΣΔ

converters. The device performs A/D conversions of analog signals on two independent

channels in parallel. The current channel is multiplexed as a primary or secondary current

channel in order to perform the tamper function, if enabled. The converted ΣΔ signals are

supplied to the internal hard-wired DSP unit, which filters and integrates these signals in

order to boost the resolution and to yield all the necessary signals for the computations. A

ΣΔ modulator converts the input signal into a continuous serial stream of 1’s and 0’s at a

rate determined by the sampling clock. In the STPM10, the sampling clock is equal to

fCLK/4. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC

output is subtracted from the input signal. If the loop gain is high enough, the average value

of the DAC output (and therefore the bit stream) can approach that of the input signal level.

When a large number of samples are averaged, a very precise value for the analog signal

is obtained. This averaging is carried out in the DSP section, which implements decimation,

integration and DC offset cancellation of the supplie

d ΣΔ signals. The gain of the

decimation filters is 1.004 for the voltage channel and 0.502 for the current channel. The

resulting signal has a resolution of 11 bits per voltage channel and 16 bits per current

channel.

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