STPM10 datasheet(21/47 Pages) STMICROELECTRONICS

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STPM10

Theory of operation

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It means that if FRS is set and BFR is also set, all the energy computation is carried on as

BFR was cleared. In this case then p=u*i, where u could be zero or not (if BFR was set

because voltage RMS register value is below 64). When the line frequency re-enters the

nominal band, the BFR flag is automatically reset. This BFR error flag is also assembled as

part of the 8-bit status register (see Table 10: "Status bit description").

7.6

Power supply

The main STPM10 supply pin is the VCC pin. From the VCC pin two linear regulators

provide the necessary voltage for the analog part VDDA (3 V) and for the digital part VDDD

(1.8 V). The VSS pin represents the reference point for all the internal signals. A 100 nF

low ESR capacitor should be connected between VCC and VSS, VDDA and VSS, VDDD

and VSS. All these capacitors must be located very close to the device. The STPM10

contains a power on reset (POR) detection circuit. If the VCC supply is less than 2.5 V,

then the STPM10 goes into an inactive state, all the functions are blocked and a reset

condition is asserted. This is useful to ensure correct device operation at power-up and

during power-down. The power supply monitor has built-in hysteresis and filtering, which

give a high degree of immunity from false triggering due to noisy supplies. A band-gap

voltage reference (VBG) of 1.23 V ±1% is used as the reference voltage level source for

the two linear regulators and for the A/D converters. Also, this module produces several

bias currents and voltages for all other analog modules. The band-gap voltage can be

compensated regardless of the temperature variations with the BGTC bits.

Figure 17: Band-gap temperature variation

7.7

Load monitoring

The STPM10 includes a no-load condition detection circuit with adjustable threshold. This

circuit monitors the voltage and the current channels and, when the measured voltage is

below the set threshold, the internal signal BIL becomes high. Information about this signal

is also available in the status bit BIL.

The no-load condition occurs when the product of the VRMS and IRMS register values is

below a given value. This value can be set with the LTCH configuration bits. Four different

no-load threshold values can be chosen according to the two configuration bits LTCH (see

table below). When a no-load condition occurs (BIL=1) the integration of power is

suspended and the tamper module is disabled. The BIL signal can be accessed only

through the SPI interface.

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