STPM10 datasheet(32/47 Pages) STMICROELECTRONICS

32 / 47 page

Theory of operation

STPM10

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DocID17728 Rev 5

The internal registers are not directly accessible. Instead, 32 bits of transmission latches

are used to pre-load the data before being read or written to the internal registers. The

condition in which SCS, SYN and SCL inputs are set to high level determines the idle state

of the SPI interface, and no data transfer occurs.



SCS: enables SPI operation when low



SYN: operates different functions according to the status of the SCS pin. When SCS is

low, the SYN pin status selects if the SPI is in read (SYN = 1) or write mode (SYN =

0). When the SCS is high and SYN is also high, the results of the input or output data

are transferred to the transmission latches



SCL: basically the clock pin of the SPI interface. This pin function is also controlled by

the SCS status. If SCS is low, SCL is the input of the serial bit synchronization clock

signal. When SCS is high, SCL is also high, causing the idle state of the SPI



SDA: the data pin. If SCS is low, the operation of SDA is dependent on the status of

the SYN pin. If SYN is high, SDA is the output of the serial bit data (read mode). If

SYN is low, SDA is the input of the serial bit data signal (write mode). If SCS is high,

SDA is the input of the idle signal. Any pin above has an internal weak pull-up

mechanism of nominal 15 μA. This means that when a pin is not forced by external

signals, the state of the pin is logic high. A high state of any input pin described above

is considered an idle (not active) state. To let SPI operate correctly, the STPM10 must

be correctly supplied as described in Section 7.6: "Power supply"

An idle state of the SPI module is recognized when the signals of pins SYN, SCS, SCL and

SDA are in a logic high state. Any SPI operation should start from this idle state. When

SCS is active (low), signal SDATD should change its state at trailing edge of signal

SCLNLC and the signal SDATD should be stable at next leading edge of signal SCLNLC.

The first valid bit of SDATD always starts together with activation of signal SCLNLC.

7.20

Remote reset

The timing diagram of this operation is shown in the figure below. The time step can be as

short as 30 ns. The internal reset signal is called RRR. Unlike the POR, the RRR signal

does not cause the 30 ms delayed restart of the analog module, and the 120 ms delay in

the restart of the digital module. This signal does not clear the mode signals.

Figure 22: Timing to provide remote reset request

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