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STPM10 数据表(PDF) 24 Page - STMicroelectronics |
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STPM10 数据表(HTML) 24 Page - STMicroelectronics |
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24 / 47 page ![]() Theory of operation STPM10 24/47 DocID17728 Rev 5 current transformer (CT). These phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The STPM10 can calibrate these small phase errors by introducing delays on the voltage or current signal. The amount of phase compensation can be set using the 4 bits of the phase calibration register (CPH). The default value of this register is at a value of 0, which gives 0 ° phase compensation. When the 4 bits give a CPH of 15 (1111) the compensation introduced is +0.576 °. This compensates the phase shift usually introduced by the current sensor, while the voltage sensor, normally a resistor divider, does not introduce any delay. The resolution step of the phase compensation is 0.038 °. 7.11 Clock generator All the internal timing of the STPM10 is based on the CLKOUT signal. This signal can be generated in three different ways: 1. RC: this oscillator mode can be selected using the RC configuration bit. If RC = 1, the STPM10 runs using the RC oscillator. A resistor connected between CLKIN and ground sets the RC current. For 4 MHz operation, the recommended settling resistor is 12 kΩ. The oscillator frequency can be compensated using the CRC configuration bit. 2. Quartz: If RC = 0, the oscillator works with an external crystal. The recommended circuit is depicted in the figure below (b). 3. External clock: by keeping RC=0, it is also possible to feed the CLKOUT pin with an external oscillator signal. Figure 20: Different oscillator circuits with (a) quartz, (b) internal oscillator, (c) external source The clock generator is powered from an analog supply and is responsible for two tasks. The first is to retard the turn-on of some function blocks after POR in order to help smooth the start of the external power supply circuitry by keeping off all major loads. The second task of the clock generator is to provide all necessary clocks for the analog and digital parts. During this task, the MDIV configuration bit is used to inform the device about the nominal frequency value of CLKOUT. Two nominal frequency ranges are expected to be from 4.000 MHz to 4.194 MHz (MDIV = 0) or from 8.000 MHz to 8.192 MHz (MDIV = 1). 7.11.1 RC start-up procedure To use the device with RC oscillator the configuration bit RC (see Table 11: "Configuration bit map") must be set. Since the default configuration is for a crystal oscillator, when an RC oscillator is used instead and the device is supplied for the very first time it is not internally clocked and consequently the DSP is inactive. In this condition it is not possible to set RC |
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