5

Device description

5.1

Chip reset pin

The RSTB pin, active low, can block the operation of the device by forcing the digital core in reset state. After

releasing the RSTB pin, the STWLC68 re-starts and retrieves the default configuration data from the OTP. If not

used, the RSTB pin should be connected to the V1V8 or to the V1V8 rail.

5.2

Synchronous rectifier

The synchronous rectifier of the STWLC68 is a key block in charge of converting the AC input power from the

receiving coil into a DC supply rail for the following linear regulator. In principle it consists of four N-channel

MOSFETs arranged in a H-bridge, conveniently driven by a control block that monitors the voltage at the AC1

and AC2 pins to optimize the commutations and to charge the external bootstrap capacitors for the high-side

switches. Different driving schemes are possible for the switches of the rectifier and the MCU core dynamically

selects the optimal one to maximize the overall efficiency as a function of the operating point. When designing the

filtering capacitor at the output of the synchronous rectifier, it must be taken into account that it has to minimize

the AC residual ripple and to provide energy storage to sustain load transients, without impacting on the ASK

communication with the transmitter.

5.3

Main linear regulator

The main linear regulator of the STWLC68 ensures a constant output voltage with minimum power loss. Excellent

line and load regulation are demanded to the analog circuitry of this block, while the optimal operating point is

managed by the MCU core. The minimization of the power loss is achieved by adjusting the drop-out voltage

according to a programmed target curve: to do so, the MCU core handles the communication with the transmitter

to get the desired VRECT rail voltage. Key voltages and currents in the block are constantly monitored to optimize

the performance of the linear regulator and to to provide multiple proctection levels (see related section).

The main linear regulator has three independent control loops acting on the power pass element:

•

Output voltage regulation loop: this loop regulates the output voltage at the nominal value set in the

dedicated register;

•

Input current regulation loop: in order to prevent a collapse at the output of the synchronous rectifier, the

current through the linear regulator is limited to a fixed 1.5 A limit. This loop overdrives the previous one,

reducing the output voltage as a consequence.

•

Input voltage regulation loop: this loop works in conjunction with the input current one and avoids that the

VRECT rail drops below a programmable value.

Both input current and input voltage regulation loops play an important role: since the output of the rectifier is a

highly variable voltage source (especially because of unpredictable changes in coupling of the coils), extra care

is needed to avoid voltage drops that could lead to an undesirable MCU core reset. The pass transistor is an

N-channel MOSFET and the BOOT pin is dedicated to its bootstrap capacitor, ensuring correct driving and lower

on-resistance also in case of drop-out condition. A filtering capacitance higher than 20 μF has to be connected to

the output rail (VOUT) in order to ensure stable operation of the linear regulator.

5.4

ASK communication

Robust and reliable in-band ASK modulation is critical to the operation of any Qi compliant devices. STWLC68

has dedicated hardware on top of the firmware algorithm to improve the performance of the in-band

communication. Parameters controlling the ASK modulation used during communication (e.g. modulation index

as a function of the load) are programmable via OTP. At ping-up and in light-load or no-load conditions the

modulation index may result critical, especially in case of poor magnetic coupling of the coils: an internal,

programmable dummy load at VRECT can be enabled to enhance the ASK modulation, resulting is a quicker

transaction with the transmitter. The dummy current is automatically drawn from VRECT at power-up and it is

gradually reduced as the output current increases: this operation ensures a constant load baseline that exits the

game once the external load prevails.

STWLC68

Device description

DS13131 - Rev 3

page 10/32