The STWLC68 has been assigned 0x61 as 7-bit hardware address, resulting in 0xC2 and 0xC3 8-bit addresses

for write and read operations respectively. Since both SDA and SCL pins of the STWLC68 have an open-drain

output stage, the high level is determined by external pull-up resistors at system level. The pins are tolerant up

to 5 V and the pull-up resistors should be selected as a trade-off between communication speed (lower resistors

lead to faster edges) and data integrity (the input logic levels have to be guaranteed to preserve communication

reliability).

Data Validity

As shown in Figure 5, the data on the SDA line must be stable during the high period of the clock. The high and

low states of the SDA line can only change when the SCL clock signal is low.

Start and Stop Conditions

high-to-low transition of the SDA line when SCL is high, while the stop condition is a low-to-high transition of the

SDA line when SCL is high. A STOP condition must be sent before each START condition.

STWLC68

I2C interface

DS13131 - Rev 3

page 14/32