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STWLC68 数据表(PDF) 13 Page - STMicroelectronics |
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STWLC68 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 32 page ![]() Power Receiver Interface The flow-chart visible in Figure 3 reports the whole process leading to a power transfer in Base Power Profile (BPP), the only power profile supported by STWLC68 due to a maximum output power of 5 W (1.0 A @ 5 V). Figure 3. Power transfer phases for Baseline Power Profile Ping Identification & Configuration Power Transfer Extended Digital Ping Power Transfer Contract established Selection Apply Power Signal No Response / Abort Digital Ping Power Transfer Contract Violation / Unexpected Packet / Timeout No Power Transfer Contract / Unexpected Packet / Transmission Error / Timeout Power Transfer Complete In case of Qi-mode the STWLC68 goes autonomously through Selection, Ping, Identification & Configuration phases, entering Power Transfer phase if no error occurs. During the Power Transfer phase, the device sends Received-Power and Control-Error packets periodically as feedback information for the transmitter. If a critical event like over-voltage, over-current or over-temperature occurs, the STWLC68 automatically sends the End- Power-Transfer packet. When the Power Transfer is up and running, the End-Power-Transfer packet (with any response value) or any custom packet (e.g. Proprietary packet or Charge-Status packet) can be sent to the transmitter simply through commands via I2C interface. Sending a custom packet may result in a reply (either a data packet or a pattern response from the transmitter) or no reply at all: if a response is received, the content is captured and stored in specific I2C registers. Important notes: • Changing the output voltage must respect the overall system design (selected coil, transmitter type, etc.). • Output load transient response strongly depends on correct design of the output capacitors. Severe load transients may lead to temporary output voltage collapse due to the overall TX-RX response time. • A minimum output load significantly helps in increasing the signal-to-noise ratio during digital pin and it is advisable to ensure interoperability with all transmitters. For this purpose, the STWLC68 allows the user to set a dummy load (reservoir current) that is dynamically managed to fade-out when an output load is applied. • The initial load at power-up should not exceed 2.5 W, smoothly ramping-up to full power subsequently. 5.8 I2C interface The STWLC68 can operate fully independently, i.e. without being interfaced with any host controller. In applications in which the STWLC68 has to be part of the peripherals managed by the host system, the two SDA and SCL pins could be connected to the existing I²C bus. Thedevice works as an I²C slave and supports both standard (100 kbit/s) and fast (400 kbit/s) data transfer modes. Through the I²C interface, maximum device flexibility is obtained and full access to the internal resources is possible. The host controller typically polls for device status and power transfer operation, demands for custom commands execution or reconfigures the default parameters. STWLC68 I2C interface DS13131 - Rev 3 page 13/32 |
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