Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte sent to the STWLC68 is generally followed

by an acknowledge (ACK) bit. The MSB is transferred first. One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the high state of each SCL clock pulse.

Acknowledge

generated by the slave (Figure 8). The STWLC68 generates the ACK pulse (by pulling-down the SDA line during

the acknowledge clock pulse) to confirm the correct device address or the received data bytes: the missing ACK

pulse is a so-called not-acknowledge condition (NACK) and, apart specific cases, the master aborts the ongoing

ACK pulses are genarated (see Under-Voltage Lockout thresholds in the Electrical Characteristics).

Interface protocol

The interface protocol consists of (see Figure 9):

•

start condition (START)

•

7-bit device address (0x61) + R/W bit (read =1 / write =0)

•

Register pointer, high-byte

•

Register pointer, low-byte

•

Data sequence: N x (data byte + ACK)

•

Stop condition (STOP)

The register pointer (or address) byte defines the destination register to which the read or write operation applies.

When the read or write operation is finished, the register pointer is automatically incremented.

STWLC68

I2C interface

DS13131 - Rev 3

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