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LTC6563

Rev. 0

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• Increasing RLDIFF slightly reduces the signal bandwidth.

• Output voltage compliance (VCOMPLIANCE) to be

observed relative to RLDIFF , ADJ settings, and CM volt-

age . Here is an example where output voltage compli-

ance is violated:

RLDIFF = 100Ω, Tilt = VCC, ADJ1 = 1, ADJ0 = 0,

CM = 1.7V, IIN = 90µA

Output Voltage (max)

VCM +

IOUT –IOUTBAR

•

RLDIFF

Referring to Table 2 to read output current values:

Output Voltage (max)

1.7V

36mA – 6mA

•

100

= 2.45V!

The maximum output voltage must remain below VCCO

– 1V (~2.3V) to comply with the VCOMPLIANCE rating.

Possible remedies are reducing output current(s) by

using lower power ADJ settings, reducing the input APD

current, reducing the differential load, or reducing the

CM voltage.

Power Considerations

The LTC6563 has many power modes of operation. The

state of the PWRMD, OMUX and ADJ pins will dictate

the amount of current the LTC6563 will draw. Multiple

power modes are offered to allow the user to select the

appropriate one based upon the application while mini-

mizing power dissipation.

Coupling the TIA Input – AC vs DC

Although the LTC6563 can AC-couple to the detector, best

performance is achieved when DC-coupled to a negatively

biased APD. DC-coupling reduces component count while

allowing a DC current path from the APD. The LTC6563

OFFSET feature is designed to cancel DC currents. The

maximum performance for switching speeds and satura-

tion recovery occurs in this DC-coupled configuration.

When AC-coupling to the TIA input, RB, is needed to

establish a bias point for the detector. It is worth noting

that RB is a parallel path with the TIA for the APD current

to flow through and it will impact the effective signal chain

output gain.

This value of the biasing resistor and AC-coupling capaci-

tor, CAC, can potentially create a long time-constant. CAC is

chosen based on the reactance at the frequency of inter-

est. However, RB ideally should be large to avoid stealing

APPLICATIONS INFORMATION

Figure 4. AC-Coupled Detector Circuit

Table 3. LTC6563 Power Dissipation Modes. X = Don’t Care

PWRMD OMUX ADJ1 ADJ0

IVCCI (mA) IVCCO (mA) ITOTAL (mA) DESCRIPTION

4.5

0.1

4.6

LTC6563 shutdown.

24.5

45.5

LTC6563 enabled, non-selected inputs powered down, CM pin control

disabled. This setting appropriate for a Responder device in a multi-chip/

multi-channel application.

51.5

72.5

64.5

85.5

0.1

35.1

LTC6563 deselected (outputs stage off), non-selected inputs powered up.

24.5

58.5

LTC6563 enabled, non-selected inputs powered up, CM pin control active

in setting output CM voltage. This setting appropriate for a Controller

device in a multi-chip/multi-channel application.

51.5

85.5

64.5

98.5

–HV

CAC

APD

6563 F04

AC-COUPLED TIA

DC-COUPLED TIA

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