ADCMP604 datasheet(26/34 Pages) AD

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LTC6563

Rev. 0

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APPLICATIONS INFORMATION

Under these conditions, the following pin settings should

be used:

1. TERM and TERM should be left floating.

2. An external circuit capable of sinking the output cur-

rent must be used. This task is most easily accom-

plished by providing external termination to ground.

3. The CM pin

must be tied to the expected output CM

voltage. The output clamps levels are calculated from

CM and HI pins, so failure to set the CM pin properly

may result in undesired signal clamping.

When the TERM and TERM pins are left floating, the out-

put CM voltage will be solely a function of the LTC6563

ADJ setting and the external CM load. For example, with

ADJ11 setting (IO = 28mA) and 50Ω to ground on each

output, the output CM voltage will be:

VCMO = IO • RLOAD_CM = 28mA • 50Ω = 1.4V

(4)

With the CM servo loop function disabled, the LTC6563’s

CM pin should be tied to a voltage that is close to the

expected CM value (1.4V in the example stated just

above). The output clamp circuit assumes that CM is

equal to the actual output CM voltage. If this is not the

case, the clamping voltage set by the HI pin will be miscal-

culated, and undesired signal clipping may result. For this

purpose, a replica VCMO voltage can simply be generated

off the device VCC pin using kΩ range voltage division

resistors.

Increasing Output Impedance

It may be desirable to change the output termination

impedance in order to adjust the output signal ampli-

tude. In addition, the flexibility of LTC6563’s output

structure allows for impedance matching to a variety of

different loads or transmission line impedances, which

is critical for high speed signal integrity. In the following

example, the output circuit will be modified to present a

75Ω source impedance for driving a 75Ω transmission

line and ADC load.

Consider the configuration shown in Figure 11 schematic.

The output impedance of the LTC6563 is raised to 75Ω

by adding 24.9Ω resistors in series with the internal 50Ω

TERM resistors. The TIA now presents an output imped-

ance that matches the 75Ω transmission line as well as

the net ADC-side SE impedance. The transmission line

ADC-side impedance can be calculated by:

((200Ω/2) + (2 • 4.99) || 300 Ω) = 80Ω.

Let’s now take a look at the output CM voltage that per-

tains to the schematic of Figure 11, simplified in Figure 12:

Figure 11. Increasing Diff Load Resistance and Matching to 75Ω

4.99

4pF

300

0.1µF

75 TRANSMISSION LINE

6563 F11

OMUX

OUT

TERM

PWRMD

OUTPUT

STAGE

TILT

ADJ0

ADJ1

BIAS

CTRL

IO CTRL

CM CTRL

IO CTRL

VCC

LTC6563

OUTPUT SECTION

0.1µF

×2

×1

OUTPUT

CLAMPS

CM CONROL

LOOP

HI CTRL

–

75 TRANSMISSION LINE

RS1

24.9

RS2

24.9

200

DIFF

INPUT

AD9094

VCM

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