ADCMP604 datasheet(21/34 Pages) AD

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LTC6563

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

current from the TIA path from APD signal. On one hand

large RB causes large RC time constants, while low RB

reduces the effective gain of the APD.

Another negative impact of this RC network is in the case

for saturation events. When a large signal is received from

the APD, this event will charge CAC. This will negatively

move the input bias of the TIAs and change the TIAs input

impedance to transimpedance 14kΩ. This 14kΩ coupled

with RB and CAC time constant will add the saturation

recover time. Practical values of 100pF CAC and RB of

2.2kΩ will have large saturation recovery times >1µs with

>50mA input signals. This effectively blinds the signal

chain for the next input signal.

Channel Selection

There are four TIA inputs to the LTC6563. The active chan-

nel is selected using two channel selection bits CHSEL0

and CHSEL1. When a channel is changed and PWRMD is

high, an output glitch takes <10ns to settle. When PWRMD

is low and a channel is changed, an output glitch takes

<500ns to settle. Inactive channels have 30dB of channel

to channel isolation at 400MHz when PWRMD pin is high.

When PWRMD is low the channel isolation is increased

to more than 48dB.

Table 4. Channel Selection

CHSEL1

CHSEL0

OMUX

ACTIVE CHANNEL

Hi-Z

DC Input Cancelation

The LTC6563 features a voltage controlled current source

for DC input current cancelation with minimal noise

impact. Identical currents are applied to each TIA input.

The maximum current cancelation is 200μA. The OFFSET

pin was designed to accommodate external closed loop

design for fast settling and fast switching times. See

IOFFSET vs VOFFSET curve for the transfer function. It is

recommended to use a high-speed DAC to control the

OFFSET pin.

Output MUXing

Refer to Figure 6 schematic. The output multiplexing

(OMUX) requires at least one additional LTC6563 devices

to operate in a Controller/Responder relationship. To mul-

tiplex multiple LTC6563’s they need to share a DC connec-

tion at their outputs. The controller LTC6563 (U1) output

stage needs to be connected to the internal termination

resistors. For the CM control to function, the controller

PWRMD pin must remain HIGH during the time any of

the inputs of all the parallel network are enabled. That is

because the CM servo loop is disabled if PWRMD is deas-

serted (low). The controller LTC6563 output circuit (U1)

will control the common mode for all the multiplexing.

All CM pins (U1-U4) are to be connected to the common

mode of the ADC. If the output clamping feature (HI pin)

is implemented, all CM pins (U1-U4) need to be connected

to the same voltage for proper operation. Also, tie all HI

pins (U1-U4) together and apply the required clamping

voltage to them. The HI pin is used to set the high side

clamp voltage at outputs. Internal circuity generates a

symmetric low side clamp voltage with respect to the

common mode voltage VCM.

Maximum output high side voltage = HI pin voltage

Minimum output low side voltage = VCM – (HI – VCM) =

2VCM – HI

Setting the Output CM Voltage

The LTC6563 can set the output Common Mode (CM)

voltage using the CM input pin provided on the device.

Figure 5. Recommended DC Cancel Circuit

R/W

GND

IOUT2

IOUT1

RFB

VDD

AD5424

D7-D0

ADA4851-1

LTC6563

OFFSET PIN

FPGA IO

VCC

6563 F03

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