LTC6563

27

Rev. 0

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APPLICATIONS INFORMATION

Figure 12. TIA 75Ω Matched Load Equivalent Circuit

Figure 13. CM Half-Circuit Equivalent Circuit for 75Ω Load

As in the previous cases, for analysis purposes, it is useful

to break the output load circuit into its equivalent half-

circuit to compute how the CM voltage is affected, as

shown in Figure 13.

6563 F12

I1

I2

50

50

200

R1

300

R2

300

OUT

OUT

TERM

TERM

LTC6563

2 TO

OPEN

24.9

24.9

I1

50

4 TO

OPEN

OUT

TERM

LTC6563

6563 F13

24.9

Table 6. CM Minimum Voltage and Other Operating Performance Values for Various ADJ Settings of Figure 11

ADJ1

ADJ0

CM/AVERAGE OUTPUT

RT (kΩ)

ADC FS DIFF VOLTAGE

SWING WITH FULL

MIN CM VOLTAGE (mV)

0

0

7

8.3

750

553

0

1

14

16.7

1500

1106

1

0

21

25.0

2250*

1659

1

1

28

33.3

3000*

2212*

*Limited by output voltage compliance

output CM voltage.

Table 6 shows the computed minimum CM voltage, TIA

gain (RT), and ADC FS diff voltage swing for various ADJ

settings applied to the Figure 11 configuration.

Here is a sample calculation of the values in Table 6, related

to the Figure 11 schematic, for ADJ 00 as an illustration:

a. Output current values (ADJ 00) with max input current

of 90µA (from Table 2): 12mA, 2mA

b. Net diff output load: 75Ω (37.5Ω on each output)

c.

RT Calculation: RT(k

Ω) =

37.5

Ω[(12mA – 2mA) – (2mA – 12mA)]

90µA

= 8.3kΩ

d. ADC FS diff voltage calculation = 90µA • 8.3kΩ =

series with the TERM pin, 50Ω is the TERM internal

value

In the Figure  11 schematic and tabulated results in

Table 6, the ADJ 11 setting’s Min CM voltage is too high

to be usable. Thus, the technique of lowering CM voltage

(Detailed Example 2) discussed earlier can be employed

As before, the CM circuit is not affected by the R1, R2 or

the ADC differential input impedance of 200Ω. The output

CM will be given by:

(5)