ADE7978 datasheet(80/125 Pages) AD

80 / 125 page

ADE7978/ADE7933/ADE7932/ADE7923

Data Sheet

Rev. D | Page 80 of 125

INTERRUPTS

The ADE7978 has two interrupt pins, IRQ0 and IRQ1. Each

pin is managed by a 32-bit interrupt mask register, MASK0

(Address 0xE50A) and MASK1 (Address 0xE50B), respectively.

To enable an interrupt, the appropriate bit in the MASKx register

must be set to 1. To disable an interrupt, the bit must be cleared

to 0. Two 32-bit status registers, STATUS0 (Address 0xE502) and

STATUS1 (Address 0xE503), are associated with the interrupts.

When an interrupt event occurs in the ADE7978, the correspond-

ing flag in the status register is set to Logic 1 (see Table 45 and

Table 46). If the mask bit for the interrupt in the interrupt mask

the status registers are set regardless of the state of the mask bits.

To determine the source of the interrupt, the microcontroller

(MCU) reads the corresponding STATUSx register to identify

which bit is set to 1. To clear the flag in the status register, the

MCU writes back to the STATUSx register with the flag set to 1.

After an interrupt pin goes low, the status register is read and

the source of the interrupt is identified. A 1 is written back to

the status register to clear the status flag to 0. The IRQx pin

remains low until the status flag is cleared.

By default, all interrupts are disabled with the exception of the

RSTDONE interrupt. This interrupt cannot be disabled (masked)

and, therefore, Bit 15 (RSTDONE) in the MASK1 register has no

function. The IRQ1 pin always goes low and Bit 15 (RSTDONE)

in the STATUS1 register is always set to 1 when a power-up

or a hardware/software reset ends. To cancel the status flag, the

STATUS1 register must be written with Bit 15 (RSTDONE)

set to 1.

Certain interrupts are used in conjunction with other status

registers. When the STATUSx register is read and one of the bits

listed in Table 31 to Table 35 is set to 1, the status register asso-

ciated with the bit is immediately read to identify the phase that

triggered the interrupt. Only after reading the associated status

set to 1.

Table 31 lists the bits in the MASK0 register that work with bits

in the PHSIGN register (Address 0xE617).

Table 31. MASK0 Register Bits and PHSIGN Register Bits

MASK0 Register

(Address 0xE50A)

PHSIGN Register

(Address 0xE617)

Bits

Bit Name

Bits

Bit Name

[8:6]

REVAPx

[2:0]

xWSIGN[2:0]

[12:10]

REVRPx

[6:4]

xVARSIGN[2:0]

REVPSUM1

SUM1SIGN

REVPSUM2

SUM2SIGN

REVPSUM3

SUM3SIGN

Table 32 lists the bits in the MASK1 register that work with bits

in the PHNOLOAD register (Address 0xE608).

Table 32. MASK1 Register Bits and PHNOLOAD Register Bits

MASK1 Register

(Address 0xE50B)

PHNOLOAD Register

(Address 0xE608)

Bits

Bit Name

Bits

Bit Name

NLOAD

[2:0]

NLPHASE[2:0]

FNLOAD

[5:3]

FNLPHASE[2:0]

VANLOAD

[8:6]

VANLPHASE[2:0]

Table 33 lists the bits in the MASK1 register that work with bits

in the PHSTATUS register (Address 0xE600).

Table 33. MASK1 Register Bits and PHSTATUS Register Bits

MASK1 Register

(Address 0xE50B)

PHSTATUS Register

(Address 0xE600)

Bits

Bit Name

Bits

Bit Name

Sag

[14:12]

VSPHASE[2:0]

[5:3]

OIPHASE[2:0]

[11:9]

OVPHASE[2:0]

Table 34 and Table 35 list the bits in the MASK1 register that

work with bits in the IPEAK register (Address 0xE500) and the

VPEAK register (Address 0xE501).

Table 34. MASK1 Register Bits and IPEAK Register Bits

MASK1 Register

(Address 0xE50B)

IPEAK Register

(Address 0xE500)

Bits

Bit Name

Bits

Bit Name

PKI

[26:24]

IPPHASE[2:0]

Table 35. MASK1 Register Bits and VPEAK Register Bits

MASK1 Register

(Address 0xE50B)

VPEAK Register

(Address 0xE501)

Bits

Bit Name

Bits

Bit Name

PKV

[26:24]

VPPHASE[2:0]

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