ADE7978 datasheet(22/125 Pages) AD

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ADE7978/ADE7933/ADE7932/ADE7923

Data Sheet

Rev. D | Page 22 of 125

ADE7932/

ADE7933

TOP VIEW

(Not to Scale)

VDDISO 1

GNDISO 2

V2P 3

V1P 4

GND

VDD

EMI_CTRL

V2/TEMP

RESET_EN

IM 6

DATA

IP 7

XTAL2

LDO

XTAL1

REF

SYNC

GNDISO 10

GND

Figure 12. Pin Configuration, ADE7933/ADE7932

Table 15. Pin Function Descriptions, ADE7933/ADE7932

Pin No.

Mnemonic

Description

VDD

ISO

Isolated Secondary Side Supply Voltage. This pin provides access to the 2.8 V on-chip isolated power supply.

Do not connect active external circuitry to this pin. Decouple this pin with a 10 µF capacitor in parallel with a

ceramic 0.1 µF capacitor.

2, 10

GND

ISO

Ground Reference for the Isolated Secondary Side. This pin provides the ground reference for the analog

circuitry. Use this quiet ground reference for all analog circuitry.

3, 4, 5

V2P, V1P, VM

Analog Inputs for the Voltage Channels. These channels are used with voltage transducers and are referred to in

this data sheet as the voltage channels. These inputs are pseudo differential voltage inputs with a maximum

signal level of ±0.5 V with respect to VM for specified operation. Use these pins with the related input circuitry,

as shown in Figure 42. The second voltage channel (V2) is available on the ADE7933 only. If the V1P or V2P pin

is not used on the ADE7933, connect the unused pin to the VM pin. On the ADE7932, the V2P pin must always

be connected to the VM pin.

6, 7

IM, IP

Analog Inputs for the Current Channel. This channel is used with shunts and is referred to in this data sheet as

the current channel. These inputs are pseudo differential voltage inputs with a maximum differential level of

±31.25 mV. Use these pins with the related input circuitry, as shown in Figure 42.

LDO

2.5 V Output of the Analog Low Dropout (LDO) Regulator. Decouple this pin with a 4.7 µF capacitor in parallel

with a ceramic 100 nF capacitor using GND

ISO (Pin 10). Do not connect active external circuitry to this pin.

REF

Voltage Reference. This pin provides access to the on-chip voltage reference. The on-chip reference has a

nominal value of 1.2 V. Decouple this pin to GND

ISO (Pin 10) with a 4.7 µF capacitor in parallel with a ceramic

100 nF capacitor.

11, 20

GND

Primary Ground Reference.

SYNC

Synchronization Pin. The 1.024 MHz clock signal generated by the ADE7978 SYNC pin is used for serial

communication between the ADE7933/ADE7932/ADE7923 and the ADE7978. Connect the ADE7933/ADE7932

SYNC pin to the SYNC pin of the ADE7978.

XTAL1

Master Clock. Connect this pin to the ADE7978 CLKOUT pin. The clock frequency for specified operation is

4.096 MHz. When the ADE7933/ADE7932/ADE7923 and the ADE7978 are used as a chipset, the

ADE7933/ADE7932 must function synchronously with the ADE7978; therefore, the XTAL1 pin of the

ADE7933/ADE7932 must be connected to the CLKOUT pin of the ADE7978. If the ADE7933/ADE7932 are used as

standalone chips, a crystal with a maximum drive level of 0.5 mW and an ESR of 20 Ω can be connected across

XTAL1 and XTAL2 to provide a clock source for the ADE7933/ADE7932. The clock frequency for specified

operation is 4.096 MHz, but lower frequencies down to 3.6 MHz can be used. For more information, see the

ADE7978, ADE7933/ADE7932, and ADE7923 Clocks section.

XTAL2

Leave this pin open when the ADE7933/ADE7932 are used with the ADE7978. If the ADE7933/ADE7932 are used

as standalone chips, a crystal with a maximum drive level of 0.5 mW and an ESR of 20 Ω can be connected across

XTAL1 and XTAL2 to provide a clock source for the ADE7933/ADE7932.

DATA

Data Output for Communication with the ADE7978. Connect the DATA pin to one of the following pins on the

ADE7978: DATA_A, DATA_B, DATA_C, or DATA_N. Connect the DATA pin of the Phase A ADE7933/ADE7932 to

the DATA_A pin of the ADE7978, and so on.

RESET_EN

Reset Input Enable, Active Low. The ADE7933/ADE7932 are reset by setting the RESET_EN pin low and toggling

the V2/TEMP pin four times with a frequency of 4.096 MHz. The reset ends when this pin and the V2/TEMP pin

are set high (see the Hardware Reset section).

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