ADE7978 datasheet(85/125 Pages) AD

85 / 125 page

Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 85 of 125

4. If I2C communication is used, lock the port by writing a 1 to

Bit 0 (I2C_LOCK) of the CONFIG2 register (Address 0xEA00).

If SPI communication is used, lock the port by writing any

value to the CONFIG2 register. After the serial port is locked

to I2C or SPI, the communication protocol can be changed

only after a power-down or hardware reset operation.

5. Initialize the AIGAIN, BIGAIN, CIGAIN, and NIGAIN

registers (Address 0x4380, Address 0x4383, Address 0x4386,

and Address 0x4389, respectively).

6. Start the DSP by writing 0x0001 to the run register

(Address 0xE228). For more information, see the Digital

Signal Processor section.

7. Initialize the DSP RAM-based registers located at

Address 0x4380 to Address 0x43BF. Write the last register

in the queue three times.

8. Initialize the hardware-based configuration registers

located at Address 0xE507 to Address 0xEA04 with the

exception of the CFMODE register (see Step 11).

9. Enable the DSP RAM write protection by writing 0xAD to the

internal 8-bit register located at Address 0xE7FE. Then write

0x80 to the internal 8-bit register located at Address 0xE7E3.

For more information, see the Digital Signal Processor section.

10. Read the energy registers xWATTHR, xVARHR,

xFWATTHR, xFVARHR, and xVAHR to erase their contents

and start energy accumulation from a known state.

11. Clear Bit 9 (CF1DIS), Bit 10 (CF2DIS), and Bit 11 (CF3DIS)

in the CFMODE register (Address 0xE610) to enable pulses

at the CF1, CF2, and CF3 pins.

12. Read back all ADE7978 registers to ensure that they are

initialized with the desired values.

HARDWARE RESET

When the RESET pin of the ADE7978 is set low, the ADE7978

enters the hardware reset state (see Figure 108). In the hardware

reset state, the following events take place:

•

The CLKOUT pin of the ADE7978 stops generating the

clock and is set high. The SYNC, RESET_EN, VT_A,

VT_B, VT_C, and VT_N pins are set high.

•

The dc-to-dc converter of the ADE7933/ADE7932 stops

working because the clock signal at the ADE7933/ADE7932

XTAL1 pin is high.

•

The Σ-Δ modulators on the isolated side of the ADE7933/

ADE7932 are not powered and stop working. The Σ-Δ

modulators on the ADE7923 remain powered.

During a hardware reset, the ADE7978 generates signals to reset

the ADE7933/ADE7932 and ADE7923 devices. When the

ADE7978 RESET pin is toggled high again after at least 10 µs, the

ADE7978 RESET_EN pin goes low, and the VT_A, VT_B,

VT_C, and VT_N pins toggle eight times from high to low at a

frequency of 4.096 MHz (CLKIN/4). These actions reset the

ADE7933/ADE7932 and ADE7923 devices. When the

RESET_EN pin is taken high, the ADE7978 starts generating

4.096 MHz (CLKIN/4) at the CLKOUT pin. This signal clocks

the ADE7933/ADE7932 and ADE7923 devices and they

become operational.

The ADE7978 signals the end of a reset by pulling the IRQ1

interrupt pin low and by setting Bit 15 (RSTDONE) in the

STATUS1 register (Address 0xE503) to 1. This bit is set to 0

during the reset and is set to 1 when the reset ends. Write a 1 to

the RSTDONE status bit to clear the bit. The IRQ1 pin returns

high, and the ADE7978, ADE7933/ADE7932 and ADE7923

devices are operational.

Because the I2C port is the default serial port of the ADE7978, it

becomes active after a reset. If SPI is the port used by the external

microprocessor, the procedure to enable SPI must be repeated

immediately after the RESET pin is toggled back to high (for

more information, see the Serial Interface Selection section).

After a hardware reset, all registers in the ADE7978 are reset

to their default values, and the DSP is in idle mode. Reinitialize

all ADE7978 registers, enable the DSP RAM write protection,

and start the DSP, as described in the Initializing the Chipset

section (Step 5 to Step 12). For more information about data

memory RAM protection and the run register, see the Digital

Signal Processor section.

ADE7933/ADE7932 AND ADE7923 ARE RESET

ADE7978 RESET PIN

• ADE7978 ENTERS RESET

• ADE7978 CLKOUT, SYNC, RESET_EN, VT_A,

VT_B, VT_C, VT_N PINS SET HIGH

• ADE7933/ADE7932 DC-TO-DC CONVERTERS,

Σ-Δ MODULATORS STOP WORKING

• ADE7978 RESET_EN PIN SET LOW

• ADE7978 VT_A, VT_B, VT_C, VT_N PINS

TOGGLE HIGH TO LOW 8 TIMES AT 4.096MHZ

•

• ADE7978 RESET_EN PIN SET HIGH

• ADE7978 GENERATES 4.096MHZ CLOCK AT CLKOUT PIN

AT LEAST 10µs

•RSTDONE INTERRUPT TRIGGERED

•ADE7978, ADE7933/ADE7932 AND ADE7923 READY

ADE7933/ADE7932 START WORKING

50ms

10ms

Figure 108. ADE7978/ADE7933/ADE7932 and ADE7923 Chipset During Hardware Reset

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