ADGM1304

Data Sheet

Rev. G | Page 10 of 34

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. EXPOSED PAD 1. EP1 IS INTERNALLY CONNECTED TO AGND.

IT IS RECOMMENDED TO CONNECT TO BOTH AGND AND REFGND.

2. EXPOSED PAD 2. EP2 IS INTERNALLY CONNECTED TO RFGND.

IT IS RECOMMENDED TO CONNECT TO BOTH REFGND AND AGND.

IN1/SDI

IN2/CS

IN3/SCLK

IN4/SDO

EP1

EP2

AGND

REFGND

REFGND

RFC

RFGND

RFGND

1

2

3

4

5

17

16

15

14

13

ADGM1304

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

IN1/SDI

Parallel Logic Digital Control Input 1. The voltage applied to this pin controls the gate of the RF1 to RFC

MEMS switch. In parallel mode, if the IN1 pin is low, the RF1 to RFC switch is open (off). If the IN1 pin is high,

the RF1 to RFC switch is closed (on). In SPI mode, this pin is the serial data input (SDI) pin.

2

IN2/CS

Parallel Logic Digital Control Input 2. The voltage applied to this pin controls the gate of the RF2 to RFC

MEMS switch. In parallel mode, if IN2 is low, the RF2 to RFC switch is open (off). If IN2 is high, the RF2 to RFC

switch is closed (on). In SPI mode, this pin is the chip select (CS ) pin. CS is an active low signal that selects

the slave device with which the master device intends to communicate. Typically, there is a dedicated CS

between the master device and each slave device. The CS pin also functions to synchronize and frame the

communications to and from the slave device.

3

IN3/SCLK

Parallel Logic Digital Control Input 3. The voltage applied to this pin controls the gate of the RF3 to RFC

MEMS switch. In parallel mode, if IN3 is low, the RF3 to RFC switch is open (off). If IN3 is high, the RF3 to RFC

switch is closed (on). In SPI mode, this pin is the serial clock (SCLK) pin that synchronizes the slave device(s)

to the master device. Typically, the SCLK signal is shared for all slave devices on the serial bus. The SCLK

signal is always driven by the master device.

4

IN4/SDO

Parallel Logic Digital Control Input 4. The voltage applied to this pin controls the gate of the RF4 to RFC

MEMS switch. In parallel mode, if IN4 is low, the RF4 to RFC switch is open (off). If IN4 is high, the RF4 to RFC

switch is closed (on). In SPI mode, this pin is the serial data output (SDO) pin. Typically, the SDO pin is

shared for all slave devices on the serial bus. The SDO pin is driven by only one slave device at a time,

otherwise it is high impedance. The SDO pin is always high impedance when CS is deasserted high.

5, 8, 22

AGND

Analog Ground Connection.

6

PIN/SPI

Parallel Mode Enable/SPI Mode Enable. The SPI interface is enabled when this pin is high, and the parallel

interface (IN1, IN2, IN3, IN4) is enabled when this pin is low.

7

EXTD_EN

External Voltage Drive Enable. In normal operation, set EXTD_EN low to enable the built in 10 MHz

oscillator, which enables the internal driver IC voltage boost circuitry. Setting EXTD_EN high disables the

internal 10 MHz oscillator and driver boost circuitry. With the oscillator disabled, the switch can still be

with 80 V dc from an external voltage supply. In this mode, the ADGM1304 only consumes 50 µA

maximum supply current. Disabling the internal oscillator eliminates the associated 10 MHz noise

feedthrough from the switch.

9, 11, 13, 14, 16,

17, 19, 21

RFGND

RF Ground Connection.

10

RF4

RF4 Port. This pin can be an input or an output. If unused, the pin must be connected to RFGND or terminate the

pin with a 50 Ω resistor to RFGND.

12

RF3

RF3 Port. This pin can be an input or an output. If unused, the pin must be connected to RFGND or terminate

the pin with a 50 Ω resistor to RFGND.

15

RFC

Common RF Port. This pin can be an input or an output.

18

RF2

RF2 Port. This pin can be an input or an output. If unused, the pin must be connected to RFGND or terminate

the pin with a 50 Ω resistor to RFGND.