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Data Sheet

ADGM1304

Rev. G | Page 23 of 34

THEORY OF OPERATION

The ADGM1304 is an SP4T switch fabricated using Analog

Devices MEMS switch technology. This technology enables

high power, low loss, low distortion GHz switches for use in

demanding RF applications.

Figure 47 shows a stylized cross section graphic of the switch

with dimensions. The switch is an electrostatically actuated

cantilever beam connected in a 3-terminal configuration.

Functionally, the switch is analogous to a field effect transistor

(FET), and the terminals can be used as a source, gate, and

drain.

SILICON

SOURCE

DRAIN

CANTILEVER BEAM

GATE

CONTACT GAP

METAL

Figure 47. Cross Section of the MEMS Switch Design Showing the Cantilever

Switch Beam (Not to Scale)

When a dc actuation voltage is applied between the gate

electrode and the source (the switch beam), an electrostatic

force is generated, which attracts the beam toward the

substrate. A separate on-board charge pump IC generates the

bias voltage, and 80 V is used for actuation.

When the bias voltage between the gate and the source exceeds

the threshold voltage of the switch, VTH, the contacts on the

beam touch the drain, which completes the circuit between the

source and the drain and turns the switch on. When the bias

voltage is removed (0 V on the gate electrode), the beam acts as

a spring to generate a sufficient restoring force to open the

connection between the source and the drain, break the circuit,

and turn the switch off.

Figure 48 shows the SP4T MEMS switch and controller die

within the LFCSP. Some of the LFCSP plastic molding material

is removed to allow the MEMS switch die (right) and controller

die (left) with associated wire bonds to be visible. The silicon

hermetically sealed cap covering the switch die is the black

rectangle on the right. Hermetically sealing the switches

improves the reliability and lifetime of the switches by keeping

them in a controlled atmosphere. The switch contacts do not

suffer from dry switching or low power switching lifetime

degradation.

Figure 48. ADGM1304 LFCSP Package with Molding Compound Partially

Removed to Show MEMS Switch Die (Right), Controller Die (Left), and

Associated Wire Bonds

PARALLEL DIGITAL INTERFACE

The ADGM1304 is controlled via a parallel interface. Standard

CMOS/LVTTL signals applied through this interface control

the actuation and release of all the switch channels of the

ADGM1304. Applied gate signals are boosted to give the

required voltages needed to actuate the MEMS switches.

Setting the PIN/SPI pin low enables the parallel digital interface

in 4-wire SP4T mode. In parallel mode, Pin 1 to Pin 4 (IN1 to

IN4) control the switching functions of the ADGM1304. When

a Logic 1 is applied to one of these pins, the gate of the

corresponding switch is activated and the switch turns on.

Conversely, when a Logic 0 is applied to one of these pins, the

switch turns off. Note that it is possible to connect more than

one RFx input to RFC at a time. Table 6 is the truth table for the

ADGM1304.

Table 6. Truth Table When in Parallel Digital Interface Mode

IN1

IN2

IN3

IN4

RF1 to

RFC

RF2 to

RFC

RF3 to

RFC

RF4 to

RFC

Off

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