CBTL05024BSHP datasheet(2/21 Pages) NXP

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CBTL05024

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Product data sheet

Rev. 4 — 27 March 2014

2 of 21

NXP Semiconductors

CBTL05024

High performance MUX/deMUX switch for Thunderbolt applications

 Low ON-state resistance: 13

 (typical); 16  (maximum)

 Bandwidth: 3 GHz

 Low off-state isolation:

80 dB at 5 MHz; 55 dB at 360 MHz

 Low crosstalk:

26 dB at 2.7 GHz

 Common-mode input voltage VIC: 0 V to 3.3 V

 Differential input voltage VID: 1.4 V (maximum)

 DDC channel

 ON-state resistor: 50

 (maximum)

 100 kHz 3.3 V voltage swing signal

 Both AUXIO+ and AUXIO

 outputs have 85 k (20 %) resistors

 The 85 k

 AUXIO pull-up resistor

 The 85 k

 AUXIO+ pull-down resistor is always present

2.2 DP MUX 2 : 1 switch

 Multiplexes between differential DP ML signal and LSTX/LSRX signals

 The DP ML (DisplayPort Main Link) runs up to HBR2 data rate of 5.4 Gbit/s

 The low speed DC-coupled signals LSTX and LSRX are 3.3 V single-ended signals

that operate at 1 Mbit/s

 5.4 Gbit/s DP-DPMLO path for DP MUX

 Low insertion loss for DP-DPMLO path:

1.2 dB at 2.7 GHz

 Low return loss for DP-DPMLO path:

15 dB at 2.7 GHz

 Low ON-state resistance for DP-DPMLO path: 9



 High bandwidth: 5.5 GHz

 Low off-state isolation:

20 dB at 2.7 GHz

 Low crosstalk:

25 dB at 2.7 GHz

 Common-mode input voltage VIC: 0 V to 3.3 V

 Differential input voltage VID: 1.4 V (maximum)

 LS-DPMLO path for DP MUX

 Low insertion loss: single-ended insertion loss (ON) is

1.0 dB at 5 MHz

 Low return loss: single-ended return loss (ON) is

20 dB at 5 MHz

 Low ON-state resistance: 16

 (typical) for V

DD =3.3 V

 High bandwidth: Single-ended

3 dB bandwidth is 1 GHz

 Low off-state isolation: single-ended insertion loss (OFF) is

60 dB at 5 MHz

 Low crosstalk:

40 dB at 5 GHz

2.3 General

 The input of the HPD (Hot Plug Detect) buffer is 5 V tolerant

 HPDOUT and CA_DETOUT buffers

 CA_DET input leakage current < 0.1

A to prevent driving the 1 M pull-down to a

HIGH level

 Integrated LSRX buffer with 1 M

 pull-down resistor (R1) on the LSRX buffer input

 Integrated 8.75 k

 pull-up resistor (R4) on the LSTX pin

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